поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

IP101GRI датащи(PDF) 60 Page - List of Unclassifed Manufacturers

номер детали IP101GRI
подробное описание детали  Single Port 10/100 MII/RMII/TP/Fiber Fast Ethernet Transceiver
PDF  65 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  ETC [List of Unclassifed Manufacturers]
домашняя страница  
Logo ETC - List of Unclassifed Manufacturers

IP101GRI датащи(HTML) 60 Page - List of Unclassifed Manufacturers

Back Button IP101GRI Datasheet HTML 56Page - List of Unclassifed Manufacturers IP101GRI Datasheet HTML 57Page - List of Unclassifed Manufacturers IP101GRI Datasheet HTML 58Page - List of Unclassifed Manufacturers IP101GRI Datasheet HTML 59Page - List of Unclassifed Manufacturers IP101GRI Datasheet HTML 60Page - List of Unclassifed Manufacturers IP101GRI Datasheet HTML 61Page - List of Unclassifed Manufacturers IP101GRI Datasheet HTML 62Page - List of Unclassifed Manufacturers IP101GRI Datasheet HTML 63Page - List of Unclassifed Manufacturers IP101GRI Datasheet HTML 64Page - List of Unclassifed Manufacturers Next Button
Zoom Inzoom in Zoom Outzoom out
 60 / 65 page
background image
IP101G
Data Sheet
7.4.3 RMII Timing
a. Transmit Timing Requirements
Table 17 RMII Transmit Timing Requirements
Symbol
Description
Min.
Typ.
Max.
Unit
TRMII_CLK_IN
Period of RMII clock input
-
20±50ppm -
ns
Ts
TXEN, TXD to RMII_CLK_IN setup time
4
-
-
ns
Th
TXEN, TXD to RMII_CLK_IN hold time
2
-
-
ns
Figure 21 RMII Transmit Timing Requirements
b. Receive Timing
Table 18 RMII Receive Timing Specifications
Symbol
Description
Min.
Typ.
Max.
Unit
TRMII_CLK_IN
Period of RMII clock input
-
20±50ppm -
ns
Td
2
RMII_CLK_IN rising edge to RXDV, RXD output
delay when VDDIO is 3.30V.
6
10
13
ns
Td
RMII_CLK_IN rising edge to RXDV, RXD output
delay when VDDIO is 2.50V.
6
10
16
ns
Td
RMII_CLK_IN
RXDV, RXD[3:0]
TRMII_CLK_IN
Figure 22 RMII Receive Timing Specifications
2 Timing was measured for the pin load TXEN and TXD[1:0] of IP101G. The reference 50MHz clock was from
output pin RXCLK/50M_CLKO of IP101G via the default driving current.
60/65
January 14, 2014
Copyright © 2011, IC Plus Corp.
IP101G-DS-R01



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com