IP101GRI datasheet(39/65 Pages) ETC

39 / 65 page

IP101G

Data Sheet

39/65

January 14, 2014

IP101G-DS-R01

MII page1 register23

page

MII

ROM R/W

Description

Default

23[13]

R/W RX2TX_LPBK

1= Rx to Tx loopback mode for debugging

0= Normal mode

(INTR pin of IP101G/IP101GA should pull 5.1K resistor to

DVDD33_IO for normal mode operation. We can connect INTR

pin to GND for Rx to Tx loopback test.)

23[12]

R/W Reserved

23[11]

R/W FIX_TXD_EN

1= Fix TXD pattern

0= Normal mode

23[10]

R/W FIX_TXD_SEL

1= Long pulse

0= Short pulse

23[9]

R/W FORCE_TX_LPI

1= Force TX LPI

0= TX respond to MII

23[8:0]

R/W Reserved

The other Registers are reserved registers. User is inhibited to access to these registers. It may

introduce abnormal function to write these registers.

4.9 Digital IO Pin Control Register

MII page4 Register22

page

MII

ROM R/W

Description

Default

Digital IO Pin Driving Control Register

22[15:13]

R/W RXC_DRIVE

RXC PAD Driving Current

3’b000: 1.62mA

3’b001: 3.24mA

3’b010: 4.86mA

3’b011: 6.48mA

3’b100: 8.10mA

3’b101: 12.96mA

3’b110: 17.82mA

3’b111: 22.68mA

3’b010

(e-fuse)

22[12:11]

RO Reserved

2’b00

22[10:0]

R/W Reserved

0x000

The other Registers are reserved registers. User is inhibited to access to these registers. It may

introduce abnormal function to write these registers.

MII page16 Register26~27

page

MII

ROM R/W

Description

Default

Digital IO Pin Driving Control Register

26[15]

RO Reserved

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