OPA186DBVT datasheet(30/48 Pages) TI1

30 / 48 page

8.4 Layout

8.4.1 Layout Guidelines

For best operational performance of the device, use good PCB layout practices:

• For the lowest offset voltage, avoid temperature gradients that create thermoelectric (Seebeck) effects in the

thermocouple junctions formed from connecting dissimilar conductors. Also:

– Use low thermoelectric-coefficient conditions (avoid dissimilar metals).

– Thermally isolate components from power supplies or other heat sources.

– Shield operational amplifier and input circuitry from air currents, such as cooling fans.

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp

itself. Bypass capacitors reduce the coupled noise by providing low-impedance power sources local to the

analog circuitry.

– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital

and analog grounds paying attention to the flow of the ground current. For more detailed information, see the

The PCB is a component of op amp design analog application journal.

• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output traces. If

these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed

to in parallel with the noisy trace.

• Place the external components as close as possible to the device. As Figure 8-7 shows, keep the feedback

resistor (R3) and gain resistor (R4) close to the inverting input to minimize parasitic capacitance.

• Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

• For best performance, clean the PCB following board assembly.

• Any precision integrated circuit can experience performance shifts due to moisture ingress into the plastic

package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture

introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake

at 85°C for 30 minutes is sufficient for most circumstances.

8.4.2 Layout Example

Use a low-ESR,

ceramic bypass

capacitor

Place components

close to device and to

each other to reduce

parasitic errors

Use ground pours for

shielding the input

signal pairs

–IN

V+

+IN

OUT

V–

GND

–V

Place bypass

capacitors as close to

device as possible

(avoid use of vias)

IN–

IN+

OUT

–

–IN

V+

+IN

OUT

V–

–V

OUT

IN–

IN+

Figure 8-7. Operational Amplifier Board Layout for Difference Amplifier Configuration

OPA186, OPA2186, OPA4186

SBOS968C – JUNE 2022 – REVISED JULY 2023

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