RT7207 datasheet(21/25 Pages) RICHTEK

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RT7207

DS7207-00 January 2017

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Application Information

Constant-Voltage (CV) Loop

As shown in Figure 6, the RT7207 incorporates 2 error

amplifiers (EA) inside to regulate the output voltage and

current, respectively. The output voltage is determined as :

FB1

OUT

REF_CV

FB2











For the RT7207 : The ratio of RFB1 / RFB2 is set as 7, and

it is recommended to use 91k

Ω and 13kΩ for minimizing

power loss in the resistor divider.

For the RT7207L : The ratio of RFB1 / RFB2 is set as 4, and

it is recommended to use 30k

Ω and 7.5kΩ for better

resolution of CV regulation.

Therefore, the VOUT is determined by VREF_CV, the analog

output from the DAC, and its digital counterpart, which is

controlled by the MCU, as shown in Functional Block

Diagram.

Constant-Current (CC) Loop and Current-Sense

Amplifier

The RT7207 integrates a virtually-zero input-offset-voltage

current-sense amplifier with differential-mode inputs to

minimize noise interference. The voltage gain of 20 or 40

can be set by the internal register. The amplified output

current sense signal, sent to an ADC for A/D conversion,

is monitored and processed by the MCU, and is also sent

to the CC loop. The reference voltage of the CC loop is

determined by VREF_CC (from the DAC), which is

programmed by chargers' requirements. Both the constant-

voltage and constant-current compensation loops are

connected together at the OPTO pin. The OPTO driver

sinks current through an optocoupler and an external

resistor RD from output voltage, and the optocoupler

isolates the secondary side from the primary side and

also provide the feedback compensation signal for the

primary side. Note that for better linearity of the loop

compensation range, RD should be designed to cover for

operation at the minimum output voltage.

CTR : Current transfer ratio of the optocoupler

VF : Forward voltage of the optocoupler

0.3V : The minimum OPTO voltage for the OPTO driver to

sink 2mA.

ICOMP_MAX : The maximum COMP sourcing current of a

traditional PWM controller in the primary side. It is a current

sourced from an internal bias through a built-in pull-high

resistor connected the COMP pin in the PWM controller.

Figure 6. CC and CV Loops and Current-Sense Amplifier

Power-Up Sequence

Figure 7 shows the timing diagram for the power-up

sequence. When start-up, the default output is set at 5V.

Once a Type-C cable is attached, the UFP will deliver

voltage and current settings to the RT7207 for the MCU to

decode and to program reference voltages, VREF_CV and

VREF_CC, for the CV and CC loops, which are the analog

outputs converted by the DAC. If the Type-C cable is

detached, or the output current is lower than the power-

saving mode threshold, which is typically programmed as

200mA, the RT7207 will enter power-saving mode, under

which the RT7207 operates at ultra-low operating current

and thus the total input power can be saved. If the output

current increases and exceeds the power-saving mode

threshold, or any input/output signal is toggled, the RT7207

will exit power-saving mode.

OUT _MIN

COMP _MAX

0.3V)

CTR





Io_signal

CS-

DAC

UVLO

VREF_CV

VREF_CC

VFB

OPTO

IFB

CS+

CCS

VDD (VOUT)

RFB1

RFB2

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