TAS5036APFCRG4 datasheet(27/62 Pages) TI

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Architecture Overview

SLES061B—November 2002—Revised January 2004

TAS5036A

2.4.1 Clipping Indicator

The clipping output is designed to indicate clipping. When any of the six PWM outputs exceeds the maximum

allowable amplitude, the clipping indicator is asserted. The clipping indicator is cleared every 10 ms.

2.4.2 Error Recovery

Error recovery is used to provide error management and to permit the PWM output to be reset while preserving

all intervolume, interchannel delay, dc offsets, and the other internal settings. Error recovery is initiated by

bringing the ERR_RCVRY terminal low for a minimum 5 MCLK_IN cycles or by setting the error recovery bit

in control register 1. Error recovery is a level-sensitive signal.

The device also performs an error recovery automatically:

•

When the speed configuration is changed to normal, double, or quad speed

•

Following a change in the serial data bus interface configuration

When ERR_RCVRY is brought low, all valid signals go low, and the PWM_P and PWM_M outputs go low. If

there are any pending speed configurations, these changes are then performed. When ERR_RCVRY is

brought high, a delay of 4 ms to 5 ms is performed before the system starts the output re-initialization

sequence. After the initialization time, the TAS5036A begins normal operation. During error recovery, all

controls and device settings that were not updated are maintained in their current configurations.

To permit error recovery to be used to provide TAS5100 error management and recovery, the delay between

the start of (falling edge) error recovery and the falling edge of valid 1 though valid 6 is selectable. This delay

can be selected to be either 6

µs or 47 µs.

During error recovery all serial data bus operations are ignored. At the conclusion of the sequence, the error

recovery register bit is returned to the normal operation state. Table 2−11 shows the device output signal

states during error recovery.

Table 2−11. Device Outputs During Error Recovery

SIGNAL

MODE

SIGNAL STATE

Valid 1−Valid 6

All

Low

PWM_P outputs

All

Low

PWM_M outputs

All

Low

MCLK_OUT

All

Low

SCLK

Master

Low

SCLK

Slave

Signal input

LRCLK

Master

Low

LRCLK

Slave

Signal input

SDA

All

Signal input

CLIP

All

High

The transitions are done using a quiet entrance and exit sequence to prevent pops and clicks.

2.4.3 Individual Channel Error Recovery

Individual channel error recovery is used to provide error management and to permit the PWM output to be

turned off. Error recovery is initiated by setting one or more of the six error recovery bits in the error recovery

While the error recover bits are brought low, the valid signals go to the low state. When the error recovery bits

are brought high, a delay of 4 ms to 5 ms occurs before the channels are returned to normal operation.

The delay between the falling edge of the error recover bit and the falling edge of valid 1 though valid 6 is

selectable. This delay can be selected to be either 6

µs or 47 µs.

The TAS5036A controls the relative timing of the pseudo-differential drive control signals plus the valid signal

to minimize the production of system noise during error recovery operations. The transitions to valid low and

valid high are done using an almost quiet entrance and exit sequence to prevent pops and clicks.

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