TAS5036APFCRG4 datasheet(24/62 Pages) TI

24 / 62 page

Architecture Overview

SLES061B—November 2002—Revised January 2004

TAS5036A

There is no correct number of MCLKs per LRCLK:

•

Fs error has occurred

•

LRCLK error

•

MCLK_IN count error

LRCLK is absent:

•

LRCLK error

MCLK is the wrong frequency, changing frequency, or absent:

•

DCLK phase error with respect to MCLK

•

MCLK phase error with respect to DCLK

•

PWM timing error

SCLK is the wrong frequency or absent

•

SCLK error

2.3

Signal Processing

This section contains the signal processing functions that are contained in the TAS5036A. The signal

processing is performed using a high-speed 24-bit signal processing architecture. The TAS5036A has the

following signal processing features:

•

Individual channel soft volume with a range of 24 dB to −114 dB plus mute

•

Soft mute

•

Automute

•

50-

µs/15-µs de-emphasis filter supported in the sampling rates 32 kHz, 44.1 kHz, and 48 kHz

2.3.1 Volume Control

The gain of each output can be adjusted by a soft digital volume control for each channel. Volume adjustments

are performed using a soft gain update s-curve, which is approximated using a second-order filter fit. The curve

fit is performed over a transition interval between 41 ms and 65 ms.

The volume of each channel can be adjusted from mute to −114 dB to 24 dB in 0.5 dB steps. Because of the

numerical representation that is used to control the volume, at very low volume levels the step size increases

for gains that are less than −96 dB. The default volume setting following power up or reset is 0 dB for all

channels. The step size adjustment is linear down to approximately −90 dB, see Figure 2−10.

TAS5036APFCRG4 датащи(PDF) 24 Page - Texas Instruments

TAS5036APFCRG4 датащи(HTML) 24 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

датащи скачать

ссылки URL