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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD5821 датащи(PDF) 4 Page - Analog Devices |
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AD5821 датащи(HTML) 4 Page - Analog Devices |
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4 / 16 page  AD5821 Rev. 0 | Page 4 of 16 AC SPECIFICATIONS VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance RL = 25 Ω connected to VDD, unless otherwise noted. Table 2. B Version1, 2 Parameter Min Typ Max Unit Test Conditions/Comments Output Current Settling Time 250 μs VDD = 3.6 V, RL = 25 Ω, LL = 680 μH, ¼ scale to ¾ scale change (0x100 to 0x300) Slew Rate 0.3 mA/μs Major Code Change Glitch Impulse 0.15 nA-s 1 LSB change around major carry Digital Feedthrough3 0.06 nA-s 1 Temperature range is as follows: B Version = −40°C to +85°C. 2 Guaranteed by design and characterization; not production tested. 3 See the section. Terminology TIMING SPECIFICATIONS VDD = 2.7 V to 3.6 V. All specifications TMIN to TMAX, unless otherwise noted. Table 3. B Version Parameter1 Limit at TMIN, TMAX Unit Description fSCL 400 kHz max SCL clock frequency t1 2.5 μs min SCL cycle time t2 0.6 μs min tHIGH, SCL high time t3 1.3 μs min tLOW, SCL low time t4 0.6 μs min tHD, STA, start/repeated start condition hold time t5 100 ns min tSU, DAT, data setup time t62 0.9 μs max tHD, DAT, data hold time 0 μs min t7 0.6 μs min tSU, STA, setup time for repeated start t8 0.6 μs min tSU, STO, stop condition setup time t9 1.3 μs min tBUF, bus free time between a stop condition and a start condition t10 300 ns max tR, rise time of both SCL and SDA when receiving 0 ns min May be CMOS driven t11 250 ns max tF, fall time of SDA when receiving 300 ns max tF, fall time of both SCL and SDA when transmitting 20 + 0.1 CB3 ns min CB 400 pF max Capacitive load for each bus line 1 Guaranteed by design and characterization; not production tested. 2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VINHMINof the SCL signal) to bridge the undefined region of the SCL falling edge. 3 CB is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 VDD and 0.7 VDD. Timing Diagram SDA t9 SCL t3 t10 t11 t4 t4 t6 t2 t5 t7 t1 t8 START CONDITION REPEATED START CONDITION STOP CONDITION Figure 2. 2-Wire Serial Interface Timing Diagram |
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