SST25VF080B datasheet(7/28 Pages) SST

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Data Sheet

8 Mbit SPI Serial Flash

SST25VF080B

S71296-01-000

1/06

Block Protection (BP3,BP2, BP1, BP0)

The Block-Protection (BP3, BP2, BP1, BP0) bits define the

size of the memory area, as defined in Table 4, to be soft-

ware protected against any memory Write (Program or

Erase) operation. The Write-Status-Register (WRSR)

instruction is used to program the BP3, BP2, BP1 and BP0

bits as long as WP# is high or the Block-Protect-Lock

(BPL) bit is 0. Chip-Erase can only be executed if Block-

Protection bits are all 0. After power-up, BP3, BP2, BP1

and BP0 are set to 1.

Block Protection Lock-Down (BPL)

WP# pin driven low (VIL), enables the Block-Protection-

Lock-Down (BPL) bit. When BPL is set to 1, it prevents any

further alteration of the BPL, BP3, BP2, BP1, and BP0 bits.

When the WP# pin is driven high (VIH), the BPL bit has no

effect and its value is “Don’t Care”. After power-up, the BPL

bit is reset to 0.

TABLE

4: SOFTWARE STATUS REGISTER BLOCK PROTECTION FOR SST25VF080B1

1. X = Don’t Care (RESERVED) default is “0

Protection Level

Status Register Bit2

2. Default at power-up for BP2, BP1, and BP0 is ‘111’. (All Blocks Protected)

Protected Memory Address

BP3

BP2

BP1

BP0

8 Mbit

None

Upper 1/16

F0000H-FFFFFH

Upper 1/8

E0000H-FFFFFH

Upper 1/4

C0000H-FFFFFH

Upper 1/2

80000H-FFFFFH

All Blocks

00000H-FFFFFH

All Blocks

00000H-FFFFFH

All Blocks

00000H-FFFFFH

T4.0 1296

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