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M50FLW040A датащи(PDF) 43 Page - STMicroelectronics |
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M50FLW040A датащи(HTML) 43 Page - STMicroelectronics |
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43 / 64 page ![]() M50FLW040A, M50FLW040B DC and AC parameters 43/64 Figure 13. FWH/LPC interface clock waveform IPP VPP Supply Current (Read/Standby) VPP > VCC 400 µA IPP1 (3) VPP Supply Current (Program/Erase active) VPP = VCC 40 mA VPP = 12 V ± 5% 15 mA 1. Input leakage currents include High-Z output leakage for all bidirectional buffers with three-state outputs. 2. ID3 pin is RFU in LPC mode. 3. Sampled only, not 100% tested. Table 25. FWH/LPC interface clock characteristics Symbol Parameter Test Condition Value Unit tCYC CLK Cycle Time(1) 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed by design rather than tested. Refer to PCI Specification. Min 30 ns tHIGH CLK High Time Min 11 ns tLOW CLK Low Time Min 11 ns CLK Slew Rate peak to peak Min 1 V/ns Max 4 V/ns Table 24. DC characteristics (continued) Symbol Parameter Interface Test Condition Min Max Unit AI03403 tHIGH tLOW 0.6 VCC tCYC 0.5 VCC 0.4 VCC 0.3 VCC 0.2 VCC 0.4 VCC, p-to-p (minimum) |
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