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M50FLW040A датащи(PDF) 25 Page - STMicroelectronics

номер детали M50FLW040A
подробное описание детали  4-Mbit (5 횞 64 Kbyte blocks 3 횞 16 횞 4 Kbyte sectors) 3-V supply Firmware Hub / low-pin count Flash memory
PDF  64 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M50FLW040A датащи(HTML) 25 Page - STMicroelectronics

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M50FLW040A, M50FLW040B
Bus operations
25/64
Figure 9.
LPC bus write waveforms (1 byte)
Table 9.
LPC bus write field definitions (1 byte)
Clock
Cycle
Number
Clock
Cycle
Count
Field
LAD0-
LAD3
Memory
I/O
Description
1
1
START
0000b
I
On the rising edge of CLK with LFRAME Low,
the contents of LAD0-LAD3 must be 0000b to
indicate the start of a LPC cycle.
21
CYCTYPE
+ DIR
011Xb
I
Indicates the type of cycle. Bits 3:2 must be 01b.
Bit 1 indicates the direction of transfer: 1b for
write. Bit 0 is don’t care (X).
3-10
8
ADDR
XXXX
I
A 32-bit address is transferred, with the most
significant nibble first. A23-A31 must be set to 1.
A22=1 for memory access, and A22=0 for
register access. Table 5 shows the appropriate
values for A21-A19.
11-12
2
DATA
XXXX
I
Data transfer is two cycles, starting with the
least significant nibble.
13
1
TAR
1111b
I
The host drives LAD0-LAD3 to 1111b to indicate
a turnaround cycle.
14
1
TAR
1111b
(float)
O
The LPC Flash Memory takes control of LAD0-
LAD3 during this cycle.
15
1
SYNC
0000b
O
The LPC Flash Memory drives LAD0-LAD3 to
0000b, indicating it has received data or a
command.
16
1
TAR
1111b
O
The LPC Flash Memory drives LAD0-LAD3 to
1111b, indicating a turnaround cycle.
17
1
TAR
1111b
(float)
N/A
The LPC Flash Memory floats its outputs and
the host takes control of LAD0-LAD3.
Table 10.
A/A Mux bus operations
Operation
G
W
RP
VPP
DQ7-DQ0
Bus Read
VIL
VIH
VIH
Don't Care
Data Output
Bus Write
VIH
VIL
VIH
VCC or VPPH
Data Input
Output Disable
VIH
VIH
VIH
Don't Care
Hi-Z
Reset
VIL or VIH
VIL or VIH
VIL
Don't Care
Hi-Z
AI04430
CLK
LFRAME
LAD0-LAD3
Number of
clock cycles
START
CYCTYPE
+ DIR
ADDR
DATA
TAR
SYNC
TAR
1182212



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