MPC93R52

TIMING SOLUTIONS

11

MOTOROLA

Figure 14. Output–to–output Skew tSK(O)

Figure 15. Propagation delay (t(

∅), static phase

offset) test reference

Figure 16. Output Duty Cycle (DC)

The pin–to–pin skew is defined as the worst case difference

in propagation delay between any similar delay path within a

single device

The time from the PLL controlled edge to the non controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage

VCC

VCCB2

GND

VCC

VCCB2

GND

tSK(O)

VCC

VCCB2

GND

tP

T0

DC = tP/T0 x 100%

VCC

VCCB2

GND

VCC

VCCB2

GND

t(

∅)

CCLK

FB_IN

TJIT(

∅) = |T0–T1mean|

CCLK

FB_IN

The deviation in t0 for a controlled edge with respect to a t0 mean in a

random sample of cycles

Figure 17. I/O Jitter

Figure 18. Cycle–to–cycle Jitter

Figure 19. Period Jitter

The variation in cycle time of a signal between adjacent cycles, over a

random sample of adjacent cycle pairs

The deviation in cycle time of a signal with respect to the ideal period over

a random sample of cycles

TN

TJIT(CC) = |TN–TN+1|

TN+1

TJIT(PER) = |TN–1/f0|

T0

tF

tR

VCC=3.3V

2.4

0.55

Figure 20. Output Transition Time Test Reference