MPC93R52

MOTOROLA

TIMING SOLUTIONS

6

APPLICATIONS INFORMATION

Programming the MPC93R52

The MPC93R52 supports output clock frequencies from

16.67 to 240 MHz. Different feedback and output divider

configurations can be used to achieve the desired input to

output frequency relationship. The feedback frequency and

divider should be used to situate the VCO in the frequency

lock range between 200 and 480 MHz for stable and optimal

operation. The FSELA, FSELB, FSELC pins select the

desired output clock frequencies. Possible frequency ratios

of the reference clock input to the outputs are 1:1, 1:2, 1:3, 3:2

as well as 2:3, 3:1 and 2:1. Table 1 illustrates the various

output configurations and frequency ratios supported by the

MPC93R52. See also Table 9, Table 10 and Figure 3 to

Figure 6 for further reference. A

used for feedback.

Table 9: MPC93R52 Example Configuration (F_RANGE = 0)

PLL Feedback

frefa [MHz]

FSELA

FSELB

FSELC

QA[0:4]:fref ratio

QB[0:3]:fref ratio

QC[0:1]:fref ratio

VCO

÷ 4b

50-120

0

0

0

fref

(50-120 MHz)

fref

(50-120 MHz)

fref

⋅ 2 (100-240 MHz)

0

0

1

fref

(50-120 MHz)

fref

(50-120 MHz)

fref

(50-120 MHz)

1

0

0

fref

⋅ 2÷3 (33-80 MHz)

fref

(50-120 MHz)

fref

⋅ 2 (100-240 MHz)

1

0

1

fref

⋅ 2÷3 (33-80 MHz)

fref

(50-120 MHz)

fref

(50-120 MHz)

VCO

÷ 6c

33.3-80

1

0

0

fref

(33-80 MHz)

fref

⋅3÷2 (50-120 MHz)

fref

⋅ 3 (100-240 MHz)

1

0

1

fref

(33-80 MHz)

fref

⋅3÷2 (50-120 MHz)

fref

⋅3÷2 (50-120 MHz)

1

1

0

fref

(33-80 MHz)

fref

⋅ 3 (100-240 MHz)

fref

⋅ 3 (100-240 MHz)

1

1

1

fref

(33-80 MHz)

fref

⋅ 3 (100-240 MHz)

fref

⋅3÷2 (50-120 MHz)

a.

fref is the input clock reference frequency (CCLK)

b.

QAx connected to FB_IN and FSELA=0

c.

QAx connected to FB_IN and FSELA=1

Table 10: MPC93R52 Example Configurations (F_RANGE = 1)

PLL Feedback

frefa [MHz]

FSELA

FSELB

FSELC

QA[0:4]:fref ratio

QB[0:3]:fref ratio

QC[0:1]:fref ratio

VCO

÷ 8b

25-60

0

0

0

fref

(25-60 MHz)

fref

(25-60 MHz)

fref

⋅ 2 (50-120 MHz)

0

0

1

fref

(25-60 MHz)

fref

(25-60 MHz)

fref

(25-60 MHz)

1

0

0

fref

⋅2÷3 (16-40 MHz)

fref

(25-60 MHz)

fref

⋅ 2 (50-120 MHz)

1

0

1

fref

⋅2÷3 (16-40 MHz)

fref

(25-60 MHz)

fref

(25-60 MHz)

VCO

÷ 12c

16.67-40

1

0

0

fref

(16-40 MHz)

fref

⋅3÷2 (25-60 MHz)

fref

⋅ 3 (50-120 MHz)

1

0

1

fref

(16-40 MHz)

fref

⋅3÷2 (25-60 MHz)

fref

⋅3÷2 (25-60 MHz)

1

1

0

fref

(16-40 MHz)

fref

⋅ 3 (50-120 MHz)

fref

⋅ 3 (50-120 MHz)

1

1

1

fref

(16-40 MHz)

fref

⋅ 3 (50-120 MHz)

fref

⋅3÷2 (25-60 MHz)

a.

fref is the input clock reference frequency (CCLK)

b.

QAx connected to FB_IN and FSELA=0

c.

QAx connected to FB_IN and FSELA=1