TPIC5423L

4-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL

POWER DMOS ARRAY

SLIS045 – NOVEMBER 1994

Copyright

2–1

POST OFFICE BOX 655303

description

The TPIC5423L is a monolithic gate-protected

logic-level power DMOS array that consists of four

electrically

isolated

independent

N-channel

enhancement-mode DMOS transistors. Each

transistor features integrated high-current zener

in the event that an overstress condition occurs.

These zener diodes also provide up to 4000 V of

ESD protection when tested using the human-

body model of a 100-pF capacitor in series with a

1.5-k

Ω resistor.

The TPIC5423L is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for

operation over the case temperature of – 40

°C to 125°C.

schematic

D1

DRAIN3

D3

Z1

Z3

Z2

Z4

GND

GATE3

DRAIN4

GATE4

SOURCE3

DRAIN1

GATE1

SOURCE1

DRAIN2

GATE2

Q1

Q2

Q4

Q3

D2

D4

1, 2

3

5, 6

11, 12

10

7, 8

23, 24

22

19, 20

13, 14

15

17, 18

SOURCE2

SOURCE4

4, 9, 16, 21

ZC2b

ZC2a

ZC1b

ZC1a

ZC3b

ZC3a

ZC4b

ZC4a

NOTE A: For correct operation, no terminal may be taken below GND.

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

DRAIN1

DRAIN1

GATE1

GND

SOURCE1

SOURCE1

SOURCE2

SOURCE2

GND

GATE2

DRAIN2

DRAIN2

DRAIN3

DRAIN3

GATE3

GND

SOURCE3

SOURCE3

SOURCE4

SOURCE4

GND

GATE4

DRAIN4

DRAIN4

DW PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.