TAS5036B datasheet(29/56 Pages) TI

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Architecture Overview

SLES073—February 2003

TAS5036B

7 Bit Slave Address

R/W

8 Bit Register Address (N)

8 Bit Register Data For

Address (N)

8 Bit Register Data For

Address (N)

432

Start

Stop

SDA

SCL

Figure 2–13. Typical I2C Sequence

There are no limits on the number of bytes that can be transmitted between start and stop conditions. When

the last word transfers, the master generates a stop condition to release the bus. A generic data transfer

sequence is also shown in Figure 2–13.

The 7-bit address for the TAS5036B is 001101X, where X is a programmable address bit. Using the CS0

terminal on the device, the LSB address bit is programmable to permit two devices to be used in a system.

These two addresses are licensed I2C addresses and do not conflict with other licensed I2C audio devices.

To communicate with the TAS5036B, the I2C master uses 0011010 if CS0=0 and 0011011 if CS0=1. In addition

to the 7-bit device address, an 8-bit register address is used to direct communication to the proper register

location within the device interface.

Read and write operations to the TAS5036B can be done using single byte or multiple byte data transfers.

2.5.1 Single Byte Write

As shown in Figure 2–14, a single byte data write transfer begins with the master device transmitting a start

condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction

of the data transfer. For a write data transfer, the read/write bit is 0. After receiving the correct I2C device

address and the read/write bit, the TAS5036B device responds with an acknowledge bit. Next, the master

transmits the address byte or bytes corresponding to the TAS5036B internal memory address being

accessed. After receiving the address byte, the TAS5036B again responds with an acknowledge bit. Next, the

master device transmits the data byte to be written to the memory address being accessed. After receiving

the data byte, the TAS5036B again responds with an acknowledge bit. Finally, the master device transmits

a stop condition to complete the single byte data write transfer.

R/W ACK A7

ACK

Start Condition

Stop

Condition

Acknowledge

I2C Device Address and

Read/Write Bit

Data Byte

Figure 2–14. Single Byte Write Transfer

2.5.2 Multiple Byte Write

A multiple byte data write transfer is identical to a single byte data write transfer except that multiple data bytes

are transmitted by the master device to TAS5036B as shown in Figure 2–15. After receiving each data byte,

the TAS5036B responds with an acknowledge bit.

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