6.

Memory Organization

The AT24CS32 is internally organized as 128 pages of 32 bytes each.

6.1

Device Addressing

Accessing the device requires an 8‑bit device address byte following a Start condition to enable the device for a read

or write operation. Since multiple slave devices can reside on the serial bus, each slave device must have its own

unique address so the master can access each device independently.

The Most Significant four bits of the device address byte is referred to as the device type identifier. The device type

identifier ‘1010’ (Ah) is required in bits 7 through 4 of the device address byte (see Table 6-1).

The AT24CS32 utilizes a separate memory block containing a factory programmed 128-bit serial number. Access to

this memory location is similar to the EEPROM region with the exception that the device type identifier is set to ‘1011’

(Bh) in bits 7 through 4 of the device address byte (see Table 6-1).

Following the 4-bit device type identifier are the hardware slave address bits, A2, A1 and A0. These bits can be used

to expand the address space by allowing up to eight Serial EEPROM devices on the same bus. These hardware

slave address bits must correlate with the voltage level on the corresponding hardwired device address input pins A0,

A1 and A2. The A0, A1 and A2 pins use an internal proprietary circuit that automatically biases the pin to a logic ‘0’

state if the pin is allowed to float. In order to operate in a wide variety of application environments, the pull‑down

mechanism is intentionally designed to be somewhat strong. Once the pin is biased above the CMOS input buffer's

trip point (~0.5 x VCC), the pull‑down mechanism disengages. Microchip recommends connecting the A0, A1 and A2

pins to a known state whenever possible.

When utilizing the SOT23 package, the A2, A1 and A0 pins are not accessible and are left floating. The previously

mentioned automatic pull-down circuit will set this pin to a logic ‘0’ state. As a result, to properly communicate with

the device in the SOT23 package, the A2, A1 and A0 software bits must always be set to logic ‘0’ for any operation.

Refer to Table 6-1 to review these bit positions.

The eighth bit (bit 0) of the device address byte is the Read/Write Select bit. A read operation is initiated if this bit is

high and a write operation is initiated if this bit is low.

Upon the successful comparison of the device address byte, the AT24CS32 will return an ACK. If a valid comparison

is not made, the device will NACK.

Table 6-1. Device Address Byte

Access Area

Device Type Identifier

Hardware Slave Address

Bits(1)

R/W Select

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EEPROM

1

0

1

0

A2

A1

A0

R/W

Serial Number

1

0

1

1

A2

A1

A0

R/W

Note: 

1.

The hardware slave address bits must be set to logic ‘0’ when using the SOT23 package.

For all operations except the current address read, two 8‑bit word address bytes must be transmitted to the device

immediately following the device address byte. The word address bytes consist of the 12‑bit memory array word

address, and are used to specify which byte location in the EEPROM to start reading or writing.

The first word address byte contains the four Most Significant bits of the word address (A11 through A8) in bit

positions three through zero, as seen in Table 6-2. The remainder of the first word address byte are “don’t care” bits

(in bit positions seven through five) as they are outside of the addressable 32‑Kbit range. Upon completion of the first

word address byte, the AT24CS32 will return an ACK.

AT24CS32

Memory Organization

© 2020 Microchip Technology Inc.

Datasheet

DS20006341A-page 16