7.

Write Operations

All write operations for the AT24CS32 begin with the master sending a Start condition, followed by a device address

byte with the R/W bit set to logic ‘0’, and then by the word address bytes. The data value(s) to be written to the

device immediately follow the word address bytes.

7.1

Byte Write

The AT24CS32 supports the writing of a single 8-bit byte. Selecting a data word in the AT24CS32 requires 12-bit

word address.

Upon receipt of the proper device address and the word address bytes, the EEPROM will send an Acknowledge. The

device will then be ready to receive the 8-bit data word. Following receipt of the 8‑bit data word, the EEPROM will

respond with an ACK. The addressing device, such as a bus master, must then terminate the write operation with a

Stop condition. At that time, the EEPROM will enter an internally self-timed write cycle, which will be completed within

tWR, while the data word is being programmed into the nonvolatile EEPROM. All inputs are disabled during this write

cycle, and the EEPROM will not respond until the write is complete.

Figure 7-1. Byte Write

SCL

SDA

Start Condition

by Master

Device Address Byte

First Word Address Byte

MSb

MSb

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

0

1

0

A

2

A

1

A

0

0

0

Second Word Address Byte

Data Word

Stop Condition

by Master

MSb

MSb

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

D7 D6 D5 D4 D3 D2 D1 D0

0

X

X

X

X

A11 A10 A9

A8

0

ACK

from Slave

ACK

from Slave

ACK

from Slave

ACK

from Slave

A7 A6

A5

A4

A3 A2 A1

A0

0

7.2

Page Write

A page write operation allows up to 32 bytes to be written in the same write cycle, provided all bytes are in the same

row of the memory array (where address bits A11 through A5 are the same). Partial page writes of less than 32 bytes

are also allowed.

A page write is initiated the same way as a byte write, but the bus master does not send a Stop condition after the

first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the bus master

can transmit up to thirty one additional data words. The EEPROM will respond with an ACK after each data word is

received. Once all data to be written has been sent to the device, the bus master must issue a Stop condition (see

Figure 7-2) at which time the internally self-timed write cycle will begin.

The lower five bits of the word address are internally incremented following the receipt of each data word. The higher

order address bits are not incremented and retain the memory page row location. Page write operations are limited to

writing bytes within a single physical page, regardless of the number of bytes actually being written. When the

incremented word address reaches the page boundary, the address counter will rollover to the beginning of the same

page. Nevertheless, creating a rollover event should be avoided as previously loaded data in the page could become

unintentionally altered.

AT24CS32

Write Operations

© 2020 Microchip Technology Inc.

Datasheet

DS20006341A-page 18