ST72344 datasheet(137/191 Pages) STMICROELECTRONICS

137 / 191 page

ST72340, ST72344, ST72345

137/191

Note: Read/Write interrupts are generated only after stop or restart conditions. Figure 80 shows the con-

ditions for the generation of the two interrupts.

11.7.8 Register Description

I2C 3S CONTROL REGISTER 1 (I2C3SCR1)

Read / Write

Reset Value: 0000 0000 (00h)

Bits 7:6 = PL1:0 Page length configuration

This bit is set and cleared by software. It is also

cleared by hardware when the interface is disa-

bled (PE=0).

Bit 5 = Reserved, must be kept at 0.

Bit 4 = ITER BERR / NACK Interrupt enable

This bit is set and cleared by software. It is also

cleared by hardware when the interface is disa-

bled (PE=0).

0: BERR / NACK interrupt disabled

1: BERR / NACK interrupt enabled

Note: In case of error, if ITER is enabled either in-

terrupt 1 or 2 is generated depending on which

slave flags the error (see Figure 80).

Bit 3= ITRE3 Interrupt enable on read from Slave 3

This bit is set and cleared by software It is also

cleared by hardware when interface is disabled

(PE =0).

0: Interrupt on Read from Slave 3 disabled

1: Interrupt on Read from Slave 3 enabled

Bit 2 = ITRE1/2 Interrupt enable on read from

Slave 1 or 2

This bit is set and cleared by software It is also

cleared by hardware when interface is disabled

(PE =0)

0: Interrupt on Read from Slave 1 or 2 disabled

1: Interrupt on Read from Slave 1 or 2 enabled

Bit 1= ITWE3 Interrupt enable on write to Slave 3

This bit is set and cleared by software. It is also

cleared by hardware when interface is disabled.

0: Interrupt after write to Slave 3 disabled

1: Interrupt after write to Slave 3 enabled

Bit 0 = ITWE1/2 Interrupt enable on write to Slave

1 or 2

This bit is set and cleared by software. It is also

cleared by hardware when interface is disabled

software. It is also cleared by hardware when

when interface is disabled.

0: Interrupt after write to Slave 1 or 2 disabled

1: Interrupt after write to Slave 1 or 2 enabled

I2C CONTROL REGISTER 2 (I2C3SCR2)

Read / Write

Reset Value: 0000 0000 (00h)

Bits 7:5 = Reserved, must be kept at 0.

Bit 4= WP2 Write Protect enable for Slave 2

This bit is set and cleared by software. It is also

cleared by hardware when the interface is disa-

bled (PE=0)

0: Write access to Slave 2 RAM buffer enabled

1: Write access to Slave 2 RAM buffer disabled

Interrupt Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Interrupt on write to Slave 1

WF1

ITWE1

Yes

Interrupt on write to Slave 2

WF2

ITWE1

Yes

Interrupt on write to Slave 3

WF3

ITWE2

Yes

Interrupt on Read from Slave 1, Slave 2 or Slave 3.

RF1- RF3

ITREx

Yes

Errors

BERR,

NACK

ITER

Yes

PL1

PL0

ITER

ITRE3

ITRE1/

ITWE3

ITWE

1/2

PL1

PL0

Page length

Full Page (256 bytes for slave 1 & 2, 128

bytes for slave 3)

WP2

WP1

BusyW

B/W

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