ST72340 datasheet(134/191 Pages) STMICROELECTRONICS

134 / 191 page

ST72340, ST72344, ST72345

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I2C3S INTERFACE (Cont’d)

11.7.5.4 Rollover Handling

The RAM buffer of each slave is divided into pages

whose length is defined according to PL1:0 bits in

I2C3SCR1. Rollover takes place in these pages as

described below.

In the case of Page Write, if the number of data

bytes transmitted is more than the page length, the

current address will roll over to the first byte of the

current page and the previous data will be

overwritten. This page size is configured using

PL[1:0] bit in the I2C3SCR1 register.

In case of Sequential Read, if the current address

the address will roll over to the first address of the

reserved area for the respective slave.

There is no status flag to indicate the roll over.

Note:

The reserved areas for slaves 1 and 2 have a limit

of 256 bytes. The area for slave 3 is 128 bytes.

The MSB of the address is hardwired, the

addressing master therefore needs to send only

an 8 bit address.

The page boundaries are defined based on page

size

configuration

using

PL[1:0]

bit

the

I2C3SCR1 register. If an 8-byte page size is

selected, the upper 5 bits of the RAM address are

fixed and the lower 3 bits are incremented. For

example, if the page write starts at register

address 0x0C, the write will follow the sequence

0x0C, 0x0D, 0x0E, 0x0F, 0x08, 0x09, 0x0A, 0x0B.

If a 16-byte page size is selected, the upper 4 bits

of the RAM address are fixed and the lower 4 bits

are incremented. For example if the page write

starts at register address 0x0C, the write will follow

the sequence 0x0C, 0x0D, 0x0E, 0x0F, 0x00,

0x01, etc.

11.7.5.5 Error Conditions

– BERR: Detection of a Stop or a Start condition

during a byte transfer. In this case, the BERR bit

is set by hardware with an interrupt if ITER is set.

During a stop condition, the interface discards

the data, releases the lines and waits for another

Start condition. However, a BERR on a Start

condition will result in the interface discarding the

data and waiting for the next slave address on

the bus.

– NACK: Detection of a non-acknowledge bit not

followed by a Stop condition. In this case, NACK

bit is set by hardware with an interrupt if ITER is

set.

Figure 72. Transfer Sequencing

Legend: S=Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,

WF = WF event, WFx bit is set (with interrupt if ITWEx=1, after Stop or Restart conditions), cleared by

reading the I2C3SSR register while no communication is ongoing.

RF = RF event, RFx is set (with interrupt if ITREx=1, after Stop or Restart conditions) , cleared by reading

the I2C3SSR register while no communication is ongoing.

BusyW = BusyW flag in the I2C3CR2 register set, cleared by software writing 0.

Note: The I2C3S supports a repeated start (Sr) in place of a stop condition (P).

7-bit Slave receiver:

7-bit Slave transmitter:

S Address

Data1

Data2

.....

DataN

BusyW

S Address

Data1

Data2

.....

DataN

NA P

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