ST72340 datasheet(132/191 Pages) STMICROELECTRONICS

132 / 191 page

ST72340, ST72344, ST72345

132/191

Figure 71. 16-bit Word Read Operation Flowchart

11.7.4.5 Application Note

Taking full advantage of its higher interrupt priority

Slave 3 can be used to allow the addressing mas-

ter to send data bytes as commands to the ST7.

These commands can be decoded by the ST7

software to perform various operations such as

programming the Data E2PROM via IAP (In-Appli-

cation Programming).

Slave 3 writes the command byte and other data in

the RAM and generates an interrupt. The ST7 then

decodes the command and processes the data as

decoded from the command byte. The ST7 also

writes a status byte in the RAM which the address-

ing master can poll.

11.7.5 Address Handling

As soon as a start condition is detected, the

address is received from the SDA line and sent to

the shift register. Then it is compared with the

three addresses of the interface to decode which

slave of the interface is being addressed.

Address not matched: the interface ignores it

and waits for another Start condition.

Address matched: the interface generates in se-

quence the following:

– An Acknowledge pulse

– Depending on the LSB of the slave address sent

by the master, slaves enter transmitter or receiv-

er mode.

– Send an interrupt to the CPU after completion of

the read/write operation after detecting the Stop/

Restart condition on the SDA line.

SENDS ADDRESS

AND READ BIT

DECODES I2C3SNS ADDRESS

DECODES R/W BIT

SETS READ FLAG

SENDS READ ADDRESS

RECEIVES BYTE 1

STOP CONDITION

UPDATES CURRENT ADDRESS-

ISSUES DMA REQUEST

READS 1 WORD FROM RAM

RELEASES DMA

RESETS READ FLAG

HALTS EXECUTION

RESUMES EXECUTION

SERVICES I2C3SNS INTERRUPT

READS I2C3SNS STATUS REGISTER

SHADOW REG => SHIFT REG

RECEIVES BYTE 2

DELAYS WHILE CPU

COMPLETES WORD WRITE

UPDATES STATUS + DMA CNTL

WORD MODE?

STOP?

BYTE 1 => SHIFT REG

BYTE 2 => SHADOW REG

HOST

ST7 CPU

ST7 I2C3SNS

Repeat

RAM start address depends on slave address

Byte-Pair Coherency ensured by setting Word Mode + DMA on Words

NORMAL EXECUTION

Max

3 Cycles

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