MCP65R41 datasheet(21/36 Pages) MICROCHIP

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DS20002269C-page 21

MCP65R41/6

4.0

APPLICATIONS INFORMATION

The MCP65R41/6 family of push-pull and open-drain

output comparators are fabricated on Microchip’s

state-of-the-art CMOS process. They are suitable for a

wide range of high-speed applications requiring low

power consumption.

4.1

Comparator Inputs

4.1.1

NORMAL OPERATION

The input stage of this family of devices uses three

differential input stages in parallel: one operates at low

input voltages, one at high input voltages, and one at

mid input voltages. With this topology, the input voltage

range is 0.3V above VDD and 0.3V below VSS, while

providing low offset voltage throughout the Common

mode range. The input offset voltage is measured at

both VSS - 0.3V and VDD + 0.3V to ensure proper

operation.

The MCP65R41/6 family has internally-set hysteresis

VHYST that is small enough to maintain input offset

accuracy, and large enough to eliminate the output

chattering caused by the comparator’s own input noise

voltage ENI. Figure 4-1 depicts this behavior. Input

offset voltage (VOS) is the center (average) of the

(input-referred) low-high and high-low trip points. Input

hysteresis voltage (VHYST) is the difference between

the same trip points.

FIGURE 4-1:

The MCP65R41/6

Comparators’ Internal Hysteresis Eliminates

Output Chatter Caused by Input Noise Voltage.

4.1.2

INPUT VOLTAGE AND CURRENT

LIMITS

The ESD protection on the inputs can be depicted as

shown in Figure 4-2. This structure was chosen to pro-

tect the input transistors, and to minimize the input bias

current (IB). The input ESD diodes clamp the inputs

when trying to go more than one diode drop below VSS.

They also clamp any voltages that go too far above

VDD; their breakdown voltage is high enough to allow a

normal operation, and low enough to bypass the ESD

events within the specified limits.

FIGURE 4-2:

Simplified Analog Input ESD

Structures.

In order to prevent damage and/or improper operation

of these comparators, the circuit they are connected to

limit the currents (and voltages) at the VIN+ and VIN-

pins (see Absolute Maximum Ratings†). Figure 4-3

shows the recommended approach to protect these

inputs. The internal ESD diodes prevent the input pins

(VIN+ and VIN-) from going too far below ground, and

the resistors R1 and R2 limit the possible current drawn

out of the input pin. Diodes D1 and D2 prevent the input

pin (VIN+ and VIN-) from going too far above VDD.

When implemented as shown, resistors R1 and R2 also

limit the current through D1 and D2.

-3

-2

-1

100

200

300

40 0

500

600

700

800

9 00

10 00

Time (100 ms/div)

-30

-25

-20

-15

-10

-5

VOUT

VIN-

Hysteresis

VDD = 5.0V

Bond

Pad

Bond

Pad

Bond

Pad

VDD

VIN+

VSS

Input

Stage

Bond

Pad

VIN–

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