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PS2500 2.2 GHz Fractional-N Frequency Synthesizer
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Philsar Semiconductor Inc.
146 Colonnade Road S.
Nepean, Ontario, Canada
K2E 7Y1
Tel: 613-274-0922
Fax: 613-274-0915
www.philsar.com
PMP-001-DS2 V1.2
Registers
This section describes the PS2500’s registers. All register writes are programmed address first, followed
directly with data. MSBs are entered first. On power up, all register are reset to zero.
Register Map
Register Descriptions
For more information on register loading order, see “Register Loading Order” on page 9.
Main Synthesizer Registers
Figure 4: Hex0 Main Divider Register (Write only)
Table 9: PS2500 Register Map
Address
Registera
a.
All registers are write-only.
Length
(with address bits)
H0
Main divider register
16 bits
H1
Main dividend MSB register
16 bits
H2
Main dividend LSB register
16 bits
H3
Aux divider register
16 bits
H4
Aux dividend register
16 bits
H5
Reference frequency dividers register
16 bits
H6
Control register - Phase detector/Charge pumps
16 bits
H7
Control register - Power down/Multiplexer Output select
16 bits
H8
Modulation control register
16 bits
H9
Modulation data register
16 bits
Modulation data registerb - direct input
b.
No address bits are required for modulation data. Any serial data between 2 and 12 bits long is considered modulation
data.
2
≤ length ≤ 12 bits
Main Synthesizer Divider index
A3
0
1
2
3
4
5
6
7
8
9
10
11
0
A0
A1
A2
0
0
0
X
X
X
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