PS2500 2.2 GHz Fractional-N Frequency Synthesizer
- 13 -
Philsar Semiconductor Inc.
146 Colonnade Road S.
Nepean, Ontario, Canada
K2E 7Y1
Tel: 613-274-0922
Fax: 613-274-0915
www.philsar.com
PMP-001-DS2 V1.2
Table 1: PS1200 Pin Description
Pin Label
Pin #
Type
Description
Clock
Pin 1
Digital input
Clock signal pin. When /CS is low, the register address and
data is shifted in address bits first on the Data pin on the
rising edge of Clock.
For more information, see “Serial Interface” on page 5.
Data
Pin 27
Digital input
Serial address and data input pin. Address bits are followed
by data bits.
For more information, see “Serial Interface” on page 5.
/CS
Pin 28
Digital input
Active low enable pin. Enables loading of address and data
on the Data pin on the rising edge of Clock. When /CS goes
high, data is transferred to the register indicated by the
address. Subsequent clock edges are ignored.
For more information, see “Serial Interface” on page 5.
Mod_in
Pin 2
Digital input
Alternate serial modulation data input pin. Address bits are
followed by data bits.
Mux_out
Pin 3
Digital output
Internal multiplexer output. Selects from oscillator frequency,
main or auxiliary reference frequency, main or auxiliary
divided VCO frequency, serial data out or testability signals.
This pin can be tri-stated from the General Synthesizer
Registers.
For more information, see “General Synthesizer Registers”
on page 22.
Xtalacgnd/Osc
Pin 13
Ground/Input
Reference crystal AC ground, or external oscillator
complementary input.
Xtalin/Osc
Pin 14
Input
Reference crystal input, or external oscillator differential
input.
Xtalout/NC
Pin 15
Input
Reference crystal output, or no connect.
Fvco_main
Pin 7
Input
Main VCO differential input.
/Fvco_main
Pin 8
Input
Main VCO complimentary differential input
Fvco_aux
Pin 23
Input
Auxiliary VCO differential input
/Fvco_aux
Pin 22
Input
Auxiliary VCO complimentary differential input
CPout_main
Pin 11
Analog Output
Main charge pump output. The gain of the main charge pump
phase detector can be controlled from the General
Synthesizer Registers.
LD/PSmain
Pin 9
Analog Output
Programmable output pin. Indicates main phase detector
out-of-lock as an active low pulsing open collector output (high
impedance when lock is detected), or assists the loop filter in
steering the main VCO.
This pin is configured from the General Synthesizer Registers.
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