Nexperia

74ALVT162821

20-bit bus interface D-type flip-flop; positive-edge trigger with 30 Ω termination resistors; 3-state

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

1D0, 1D1, 1D2, 1D3, 1D4,

1D5, 1D6, 1D7, 1D8, 1D9

55, 54, 52, 51, 49,

48, 47, 45, 44, 43

data inputs

1Q0, 1Q1, 1Q2, 1Q3, 1Q4,

1Q5, 1Q6, 1Q7, 1Q8, 1Q9

2, 3, 5, 6, 8,

9, 10, 12, 13, 14

data outputs

2D0, 2D1, 2D2, 2D3, 2D4,

2D5, 2D6, 2D7, 2D8, 2D9

42, 41, 40, 38, 37,

36, 34, 33, 31, 30

data inputs

2Q0, 2Q1, 2Q2, 2Q3, 2Q4,

2Q5, 2Q6, 2Q7, 2Q8, 2Q9

15, 16, 17, 19, 20,

21, 23, 24, 26, 27

data outputs

1OE, 2OE

1, 28

output enable inputs (active LOW)

1CP, 2CP

56, 29

clock pulse inputs (active rising edge)

GND

4, 11, 18, 25,

32, 39, 46, 53

ground (0 V)

VCC

7, 22, 35, 50

supply voltage

6. Functional description

Table 3. Function table

H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;

L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;

NC = no change; X = don’t care;

Z = high-impedance OFF-state;

↑ = LOW-to-HIGH clock transition.

Input

Output

Operating mode

nOE

nCP

nDn

Internal register

nQn

L

↑

l

L

L

Load and read register

L

↑

h

H

H

Hold

L

NC

X

NC

NC

H

NC

X

NC

Z

Disable outputs

H

↑

nDn

nDn

Z

74ALVT162821

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Product data sheet

Rev. 5 — 19 October 2020

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