LTC4292 datasheet(24/34 Pages) AD

24 / 34 page

Data Sheet

LTC9101-2A/LTC9102

APPLICATIONS INFORMATION

analog.com

Rev. 0 | 24 of 34

the port is powered on and reads zero at all other times. Samples

are taken continuously; a moving one second average is updated

every 100ms.

Port Voltage and VEE Readback

The LTC9101-2A/LTC9102 continuously measures the VEE voltage

with a dedicated A/D converter. This global VEE measurement

is fully synchronized to all port current measurements and can

monitor down to the LTC9102 UVLO threshold.

Temperature Readback

In addition to the overtemperature fault in the supply event register,

the LTC9101-2A also reports the die temperature of each corre-

sponding LTC9102.

Overtemperature Protection

Overtemperature protection automatically removes power from the

affected ports when the LTC9102 temperature exceeds a preset

threshold (150°C, typ.). Ports are prevented from resuming oper-

ation until the die temperature drops below a preset recovery

threshold (125°C, typ.). Refer to the LTC9101-2A software interface

data sheet for details.

Over Supply Shutdown (OSS)

The LTC9101-2A provides a low latency port shedding feature

to quickly reduce the system load when required. By allowing a

preconfigured set of ports to be turned off, the current on an over-

loaded main power supply can be reduced rapidly while keeping

high priority devices powered.

In 1-bit priority mode, each port can be configured to high or low

priority. On a rising edge of the OSS HW pin, the low priority ports

are shut down within 6.5μs.

If power is removed from a port due an OSS event, the correspond-

ing "Disconnect", "Power Good", "Power Enable", and "OSS" event

bits are set for that port or quad. Refer to the LTC9101-2A software

interface data sheet for port disable effects.

If a port is turned off through OSS, the corresponding "Detection

and Classification Enable" bits remain enabled, so the port begins

redetection.

Port Remapping

The LTC9101-2A/LTC9102 supports the ability to remap ports logi-

cally. This can be achieved by writing the appropriate values into

the port remapping register to achieve the remapping (see Table

13). By default, there is no remapping.

Table 13. Port Remapping

CODE

REMAPPING

00b

Port 1

Table 13. Port Remapping (Continued)

CODE

REMAPPING

01b

Port 2

10b

Port 3

11b

Port 4

Within a quad, any physical port can be mapped to any logical port.

Code Download

The LTC9101-2A firmware is field-upgradable by downloading and

executing firmware images.

Contact Analog Devices for code download procedures and firm-

ware images.

Firmware images are stored in a dedicated flash partition. A fully-

compliant IEEE 802.3at firmware image is preconfigured on the

LTC9101-2A. The firmware image may be overwritten by the user.

Two complete copies of the firmware image are maintained under

separate error correction code (ECC) and cyclic redundancy check

(CRC) protection for maximum data protection.

Stored Configurations

Custom I2C register map initial values may optionally be stored in

a dedicated flash partition (configuration package). When shipped

from the factory, the LTC9101-2A contains a default configuration

package, where register map initial values are as specified in the

LTC9101-2A software interface data sheet. Register map default

configurations may be stored during manufacturing bring up or

field-updated through configuration package download, and are

auto-loaded on reset.

Contact Analog Devices applications support for assistance in gen-

erating custom configuration packages. Configuration packages are

downloaded using the same code download mechanisms as firm-

ware packages. Package headers ensure configuration packages

are identified and stored in the appropriate flash partition.

If a stored configuration is used, CFG[1:0] are still required to

inform the LTC9101-2A how many LTC9102s are attached. AD[4:1]

are still required to inform the LTC9101-2A of the base I2C chip

address.

Two identical copies of the configuration image are maintained

under separate ECC and CRC protection for maximum data protec-

tion.

SERIAL DIGITAL INTERFACE

Overview

The LTC9101-2A communicates with the host using a standard

SMBus/I2C 2-wire interface. The LTC9101-2A is a slave-only de-

vice, and communicates with the host controller using standard

SMBus protocols. Interrupts are signaled to the host through INT.

LTC4292 датащи(PDF) 24 Page - Analog Devices

LTC4292 датащи(HTML) 24 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34

датащи скачать

ссылки URL