Data Sheet

LTC9101-2A/LTC9102

ELECTRICAL CHARACTERISTICS

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Rev. 0 | 8 of 34

Table 4. Electrical Characteristics (Continued)

SYMBOL

PARAMETER

CONDITIONS

MIN TYP

MAX UNITS

tOSS_IDL

OSS Idle Time

50

µs

I2C Watchdog Timer Duration

* 1.5

2

3

s

Minimum Pulse Width for Masked Shutdown

* 3

µs

Minimum Pulse Width for RESET

* 4.5

µs

I2C Timing (Note 7)

fSCLK

Clock Frequency

*

1

MHz

t1

Bus Free Time

Figure 30 (Note 9)

* 480

ns

t2

Start Hold Time

Figure 30 (Note 9)

* 240

ns

t3

SCL Low Time

Figure 30 (Note 9)

* 480

ns

t4

SCL High Time

Figure 30 (Note 9)

* 240

ns

t5

SDAIN Data Hold Time

Figure 30 (Note 9)

* 60

ns

Data Clock to SDAOUT Valid

Figure 30 (Note 9)

*

250

ns

t6

Data Set-Up Time

Figure 30 (Note 9)

* 80

ns

t7

Start Set-Up Time

Figure 30 (Note 9)

* 240

ns

t8

Stop Set-Up Time

Figure 30 (Note 9)

* 240

ns

tr

SCL, SDAIN Rise Time

Figure 30 (Note 9)

*

120

ns

tf

SCL, SDAIN Fall Time

Figure 30 (Note 9)

*

60

ns

Fault Present to INT Pin Low

(Notes 9, 10)

*

150

ns

Stop Condition to INT Pin Low

(Notes 9, 10)

*

1.5

µs

ARA to INT Pin High Time

(Note 9)

*

1.5

µs

SCL Fall to ACK Low

(Note 9)

*

250

ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any absolute

maximum rating condition for extended periods may affect device reliability and lifespan.

Note 2: This chipset includes overtemperature protection to protect the device during momentary overload conditions. Junction temperature

exceeds 140°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature

may impair device reliability.

Note 3: All currents into device pins are positive; all currents out of device pins are negative.

Note 4: The LTC9102 operates with a negative supply voltage (with respect to AGND). To avoid confusion, voltages in this data sheet are

referred to in terms of absolute magnitude.

Note 5: tDIS is the same as tMPDO defined by IEEE 802.3.

Note 6: The LTC9101-2A digital interface operates with respect to DGND. All logic levels are measured with respect to DGND.

Note 7: Guaranteed by design, not subject to test.

Note 8: The IEEE 802.3 defines MPS as the set of minimum PSE and PD input current requirements to maintain power. An LTC9101-2A/

LTC9102 port resets its MPS timer when VSENSEn – VSSKn ≥ VHOLD for tMPS and removes port power when VSENSEn – VSSKn ≥ VHOLD for a

period longer than tDIS. See the Disconnect section.

Note 9: Values measured at VIHD.

Note 10: If a fault condition occurs during an I2C transaction, the INT pin is not pulled down until a stop condition is present on the I2C bus.

Note 11: Load characteristics of the LTC9102 during Mark: 7V < (AGND – VOUTn) < 10V.

Note 12: Refer to the LTC9101-2A software interface data sheet for information on serial bus usage, and device configuration and status

registers.

Note 13: Do not source or sink current from CAP1, CAP2, CAP3, and CAP4.