Initiating Conversions

A negative transition on the converter’s HOLD

pin places the device’s analog input into the hold

mode and initiates a conversion cycle. On the

CDB5012, CDB5012A, CDB5014, CDB5016,

this input can be generated by one of two means.

First, it can be supplied through the BNC coaxial

connector appropriately labeled HOLD. Alterna-

tively, switch position 4 of the DIP-switch can be

placed in the on position, thus looping the con-

verter’s EOT output back to HOLD. This results

in continuous conversions at a fraction of the

master clock frequency (see "synchronous opera-

tion" in the converter’s data sheet).

The A/D converter’s EOT output is an indicator

of its acquisition status; it falls when the analog

input has been acquired to the specified accuracy.

If an external sampling clock is applied to the

HOLD BNC connector, care must similarly be

taken to obey the converter’s acquisition and

maximum sampling rate requirements. A more

detailed discussion of acquisition and throughput

can be found in the converter’s data sheet.

T h e CDB5 01 2, CDB5 012A, C D B5014,

CDB5016 is shipped from the factory without the

HOLD BNC input terminated for operation with

an external sampling clock. However, location

R23 is reserved for the insertion of a 51

Ω resis-

tor to eliminate reflections of the incoming clock

signal.

Voltage Reference Circuitry

T h e CDB5 01 2, CDB5 012A, C D B5014,

CDB5016 features an adjustable voltage refer-

ence which allows characterization over a wide

range of reference voltages. The circuitry consists

of a 2.5V voltage reference (1403) and an adjust-

able gain block with a discrete output stage (Figure

3). The output stage minimizes the output’s head-

room requirements allowing the reference voltage to

come within 300mV of the positive supply.

The coarse and fine trim potentiometers are fac-

tory calibrated to a reference voltage of 4.5V (a

table of output code values for a reference volt-

age of 4.5V appears in the CS5012, CS5012A,

CS5014, CS5016 data sheets). When calibrating

the reference, the voltage should be measured di-

rectly at the VREF input (pin 28) or at the un-

grounded lead of decoupling capacitor C9.

ON

Unipolar

Normal Operation

Interleaved Cal

Continuous Conversion

OFF

Bipolar

Burst Cal *

Normal

Normal

Position 1

Position 2

Position 3

Position 4

* NOTE: Use of BURST CAL is not recommended.

Figure 2. DIP-Switch Definitions

+

-

R14

C13

R15

Q1

R17

R16

C14

R18

U3

C8

VREF

VA+

Coarse

Adjust

C9

U2

+

OP-07

1403

R21

R22

R19

R20

Trim

Fine

Figure 3. Voltage Reference Circuitry

CDB5012, CDB5012A, CDB5014, CDB5016

3

DS14DB11