CS42L52 datasheet(36/82 Pages) CIRRUS

36 / 82 page

DS680A1

CS42L52

4.7

Digital Interface Formats

The serial port operates in standard I²S, Left-Justified, Right-Justified (DAC only), or DSP Mode digital in-

terface formats with varying bit depths from 16 to 24. Data is clocked out of the ADC or into the DAC on the

rising edge of SCLK.

4.7.1

DSP Mode

In DSP Mode, the LRCK acts as a frame sync for 2 data-packed words (left and right channel) input on

SDIN and output on SDOUT. The MSB is input/output on the first SCLK rising edge after the frame sync

rising edge. The right channel immediately follows the left channel.

4.8

Initialization

The CODEC enters a Power-Down state upon initial power-up. The interpolation and decimation filters, del-

ta-sigma and PWM modulators and control port registers are reset. The internal voltage reference, and

switched-capacitor low-pass filters are powered down.

LRCK

SCLK

MS B

LS B

MS B

LS B

AOUTA / AINxA

Left C han nel

R ig ht C han nel

SDOUT

SDIN

AOUTB / AINxB

MSB

Figure 16. I²S Format

LRCK

SCLK

MS B

LS B

MS B

LS B

L eft C h an nel

Rig ht C h a n nel

SDOUT

SDIN

MSB

AOUTA / AINxA

AOUTB / AINxB

Figure 17. Left-Justified Format

LRCK

SCLK

MS B

LS B

MS B

LS B

L e f t C h an n e l

R i g h t C han ne l

SDIN

AOUTL

AOUTR

Audio W ord Length (AW L)

Figure 18. Right-Justified Format (DAC only)

LRCK

SCLK

MS B

LS B

SDIN

HP/LINE OUTB

LS B

Left C h an n el

R ight C h an n el

MS B

LS B MS B

Audio Word Length (AWL)

1/fs

HP/LINE OUTA

Figure 19. DSP Mode Format)

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