CS42L52 datasheet(21/82 Pages) CIRRUS

21 / 82 page

DS680A1

CS42L52

SWITCHING SPECIFICATIONS - SERIAL PORT

(Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT CLOAD = 15 pF.)

14. After powering up the CS42L52, RESET should be held low after the power supplies and clocks are

settled.

15. See “Example System Clock Frequencies” on page 77 for typical MCLK frequencies.

Parameters

Symbol

Min

Max

Units

RESET pin Low Pulse Width

(Note 14)

MCLK Frequency (Note 15)

(See “Serial Port Clock-

ing” on page 34)

MHz

MCLK Duty Cycle

Slave Mode

Input Sample Rate (LRCK)

(See “Serial Port Clock-

ing” on page 34)

kHz

LRCK Duty Cycle

SCLK Frequency

1/tP

64•Fs

SCLK Duty Cycle

LRCK Setup Time Before SCLK Rising Edge

ts(LK-SK)

LRCK Edge to SDOUT MSB Output Delay

td(MSB)

-52

SDOUT Setup Time Before SCLK Rising Edge

ts(SDO-SK)

SDOUT Hold Time After SCLK Rising Edge

th(SK-SDO)

SDIN Setup Time Before SCLK Rising Edge

ts(SD-SK)

SDIN Hold Time After SCLK Rising Edge

Master Mode

Output Sample Rate (LRCK)

All Speed Modes

(See “Serial Port Clock-

ing” on page 34)

LRCK Duty Cycle

SCLK Frequency

SCLK=MCLK mode

1/tP

12.0000

MHz

MCLK=12.0000 MHz

1/tP

68•Fs

all other modes

1/tP

64•Fs

SCLK Duty Cycle

LRCK Edge to SDOUT MSB Output Delay

td(MSB)

-52

SDOUT Setup Time Before SCLK Rising Edge

ts(SDO-SK)

SDOUT Hold Time After SCLK Rising Edge

th(SK-SDO)

SDIN Setup Time Before SCLK Rising Edge

ts(SD-SK)

SDIN Hold Time After SCLK Rising Edge

th(SK-SDO)

ts(SD-SK)

MSB

MSB-1

LRCK

SCLK

SDOUT

SDIN

td(MSB)

ts(LK-SK)

ts(SDO-SK)

Figure 3. Serial Audio Interface Timing

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