Nexperia

74HC280; 74HCT280

9-bit odd/even parity generator/checker

VM

VM

tW

tW

10 %

90 %

0 V

VI

VI

negative

pulse

positive

pulse

0 V

VM

VM

90 %

10 %

tf

tr

tr

tf

001aad983

DUT

VCC

VCC

VI

VO

RT

RL

S1

CL

open

G

Test data is given in Table 9.

Definitions test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator

CL = Load capacitance including jig and probe capacitance

RL = Load resistance.

S1 = Test selection switch

Fig. 6. Test circuit for measuring switching times

Table 9. Test data

Input

Load

S1 position

Type

VI

tr, tf

CL

RL

tPHL, tPLH

74HC280

VCC

6 ns

15 pF, 50 pF

1 kΩ

open

74HCT280

3 V

6 ns

15 pF, 50 pF

1 kΩ

open

11. Application information

aaa-024428

8

10

9

5

12

11

6

1

13

I1

4

2

PO

PE

I2

I3

I4

I5

I6

I7

I8

I0

8

10

9

5

12

11

6

1

13

I1

4

2

PO

PE

I2

I3

I4

I5

I6

I7

I8

I0

Fig. 7. Cascaded 17-bit odd/even parity generator/checker

74HC_HCT280

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 4 — 16 August 2021

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