AD9705-EB datasheet(39/52 Pages) AD

39 / 52 page

AD9704/AD9705/AD9706/AD9707

Rev. 0 | Page 39 of 52

To perform a device self-calibration, the following procedure

can be used.

The calibration clock frequency is equal to the DAC clock

divided by the division factor chosen by the DIVSEL value. The

frequency of the calibration clock must be set to under 10 MHz

for reliable calibrations. Best results are obtained by setting

DIVSEL[2:0] (Register 0x0E, Bit 2 to Bit 0) to produce the

lowest frequency calibration clock frequency that your system

requirements allow.

Enable the calibration clock by setting the CALCLK bit

(Register 0x02, Bit 0).

Enable self-calibration by writing 0x40 to Register 0x0F.

Wait approximately 4500 calibration clock cycles. Each

calibration clock cycle is between 2 and 256 DAC clock

cycles, depending on the value of DIVSEL[2:0].

Check if the self-calibration has completed by reading the

CALSTAT bit (Register 0x0F, Bit 7). A Logic 1 indicates the

calibration has completed.

When the self-calibration has completed, write 0x00 to

Disable the calibration clock by clearing the CALCLK Bit

(Register 0x02, Bit 0).

The AD970x devices allow reading and writing of the calibration

coefficients. There are 33 coefficients in total. The read/write

feature of the coefficients could be useful for improving the results

of the self-calibration routine by averaging the results of several

calibration results and loading the averaged results back into the

device. The reading and writing routines follow.

To read the calibration coefficients

Enable the calibration clock by setting the CALCLK bit

(Register 0x02, Bit 0).

Write the address of the first coefficient (0x00) to

Set the SMEMRD bit (Register 0x0F, Bit 2) by writing 0x04

to Register 0x0F.

Read the value of the first coefficient by reading the

contents of Register 0x11.

Clear the SMEMRD bit by writing 0x00 to Register 0x0F.

Repeat Step 2 through Step 5 for each of the remaining 32

coefficients by incrementing the address by one each read.

Disable the calibration clock by clearing the CALCLK Bit

(Register 0x02, Bit 0).

To write the calibration coefficients to the device:

Enable the calibration clock by setting the CALCLK bit

(Register 0x02, Bit 0).

Set the SMEMWR bit (Register 0x0F, Bit 3) by writing 0x08

to Register 0x0F.

Write the address of the first coefficient (0x00) to

Write the value of the first coefficient to Register 0x11.

Repeat Step 2 and Step 3 for each of the remaining 32

coefficients by incrementing the address by one each write.

Clear the SMEMWR bit by writing 0x00 to Register 0x0F.

Disable the calibration clock by clearing the CALCLK bit

(Register 0x02, Bit 0).

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