AD9705-EB datasheet(32/52 Pages) AD

32 / 52 page

AD9704/AD9705/AD9706/AD9707

Rev. 0 | Page 32 of 52

SPI REGISTER DESCRIPTIONS

Table 15. SPI CTL—Register 0x00

Bit Name

Bit

Direction (I/O)

Default

Description

SDIODIR

0: SDIO pin configured for input only during data transfer (4-wire interface)

1: SDIO pin configured for input or output during data transfer (3-wire interface)

DATADIR

0: Serial data uses MSB first format

1: Serial data uses LSB first format

SWRST

1: Initiate a software reset; this bit is set to 0 upon reset completion

LNGINS

0: Use 1 byte preamble (5 address bits)

1: Use 2 byte preamble (13 address bits)

PDN

1: All analog and digital circuitry off, except serial interface

SLEEP

1: DAC output current off

CLKOFF

1: Disables internal master clock.

EXREF

0: Internal bandgap reference

1: External reference

Table 16. DATA—Register 0x02

Bit Name

Bit

Direction (I/O)

Default

Description

DATAFMT

0: Unsigned binary input data format

1: Twos complement input data format

DCLKPOL

0: Data latched on DATACLK rising edge always

1: Data latched on DATACLK falling edge (only active in DESKEW mode)

DESKEW

0: DESKEW mode disabled

1: DESKEW mode enabled (adds a register in digital data path to remove

skew in received data; one clock cycle of latency is introduced)

CLKDIFF

0: Single-ended clock input

1: Differential clock input

CALCLK

0: Calibration clock disabled

1: Calibration clock enabled

Table 17. VERSION—Register 0x0D

Bit Name

Bit

Direction (I/O)

Default

Description

VER[3:0]

[3:0]

Hardware version identifier

Table 18. CALMEM—Register 0x0E

Bit Name

Bit

Direction (I/O)

Default

Description

CALMEM[1:0]

[5:4]

Calibration memory

00: Uncalibrated

01: Self-calibration

10: Not Used

11: User input

DIVSEL[2:0]

[2:0]

000

Calibration clock divide ratio from DAC clock rate

000: /256

001: /128

110: /4

111: /2

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