AD71028

Rev. 0 | Page 7 of 20

Pin No.

Mnemonic

Input/Output

Description

40

CLK27_PA

IN

Input for 27 MHz Video Reference Clock, Processor A

41

CLK27_PB

IN

Input for 27 MHz Video Reference Clock, Processor B

42

PLL_PA

IN

Input from External PLL, Processor A

43

MCLK_PA

IN

Clock Input to Processor A

46

PLL_PB

IN

Input from External PLL, Processor B

47

MCLK_PB

IN

Clock Input to Processor B

48

DIV1_PA

OUT

PLL_PA Clock (Pin 42) Divided by 512 (DOUBLE = 1) or 1024 (DOUBLE = 0)