AD71028

Rev. 0 | Page 6 of 20

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

NC = NO CONNECT

AD71028

TOP VIEW

(Not to Scale)

DIV2_PA

1

DIV1_PB

2

DIV2_PB

3

NC

4

NC

5

AGND

OUTB–

OUTB+

AVDD

AGND

36

35

34

33

32

DGND

6

DVDD

7

ODVDD

8

NC

9

AVDD

OUTA+

OUTA–

AGND

NC

31

30

29

28

27

NC

DOUBLE

26

25

13

14

15 16

17

18

19

20

21

22

23

24

48

47

46

45

44 43

42

41

40

39

38

37

Figure 2. 48-Lead Low Profile Quad Flat Pack (LQFP)

Table 9. Pin Function Descriptions

Pin No.

Mnemonic

Input/Output

Description

1

DIV2_PA

OUT

CLK27_PA clock (Pin 40) Divided by 1125

2

DIV1_PB

OUT

PLL_PB Clock (Pin 46) Divided by 512 (DOUBLE = 1) or 1024 (DOUBLE = 0)

3

DIV2_PB

OUT

CLK27_PB Clock (Pin 41) Divided by 1125

4, 5, 9, 10, 26, 27, 39

NC

No Connection

6, 16, 44

DGND

Digital Ground

7, 13, 17, 45

DVDD

Digital Supply for DSP Core

8

ODVDD

Digital Supply for Output Buffers

11

COUT

OUT

SPI Readback

12

CDATA

IN

SPI Control Data Input

14

CCLK

IN

SPI Serial Bit Clock

15

CLATCH

IN

SPI Control Latch Signal

18

RESETB

IN

Reset Signal for Both Processors, Active Low

19

SDATA_PA

IN

Data Input to Processor A

20

BCLK_PA

IN

Bit Clock Signal for Serial Data Input to Processor A

21

LRCLK_PA

IN

Left/Right Framing Signal for Data Input to Processor A

22

SDATA_PB

IN

Data Input to Processor B

23

BCLK_PB

IN

Bit Clock Signal for Serial Data Input to Processor B

24

LRCLK_PB

IN

Left/Right Framing Signal for Data Input to Processor B

25

DOUBLE

IN

Enables Internal Clock Doubler for 12.288 MHz Input (Both Processors)

28, 32, 36

AGND

Analog Ground

29

OUTA–

OUT

Negative Analog Output, Processor A

30

OUTA+

OUT

Positive Analog Output, Processor A

31, 33

AVDD

Analog Supply

34

OUTB+

OUT

Positive Analog Output, Processor B

35

OUTB–

OUT

Negative Analog Output, Processor B

37

REFCAP

IN

Connection Point for 10 µF VREF Filter Capacitor

38

FILTCAP

IN

Connection for Noise Reduction Capacitor