LTM4710-1

11

Rev. 0

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Frequency Synchronization and Clock Input

The LTM4710-1 switching frequency can be adjusted

by synchronizing the internal PLL circuit to an external

square wave clock applied at the MODE pin. The syn-

chronization frequency range is 1.2MHz to 2.6MHz. The

external clock amplitude must be greater than 1.2V and

less than 0.4V.

The internal PLL starts up at the 2MHz default frequency.

After detecting an external clock on the first rising edge

of the MODE pin, the internal PLL gradually adjusts its

operating frequency to match the frequency and phase

of the MODE signal.

Multiphase Operation

For output loads that demand more than 8A of current,

multiple LTM4710-1 channels can be paralleled to run out

of phase to provide more output current without increas-

ing input and output voltage ripples. Table 3 shows the

configuration for multiphase operation.

Table 3. LTM4710-1 Multiphase Configuration

PHASE

RT

PIN

FB

PIN

MODE

PIN

SWITCHING

FREQUENCY

Main

VIN

VOUT

Divider

Clock

Input

External Clock

Main

Resistor to

AGND

VOUT

Divider

Clock

Output

RT Programmed

Subordinary

VIN Divider

VIN

Clock Input

External Clock

To parallel multiple LTM4710-1 channels to achieve the

same switching frequency, perfect interleaved phase shift

and accurate current sharing between different channels,

one of the LTM4710-1 channels will become the main

channel, and the rest of the LTM4710-1 channels need to

be programmed as the subordinary channels.

Connecting the RT pin of the main phase to a resistor to

AGND programs the frequency and configures the MODE

pin to become the clock output used to drive the MODE

pin of the subordinary phase(s).

Connecting the RT pin of the main phase to VIN configures

the MODE pin to become an input capable of accepting

an external clock.

APPLICATIONS INFORMATION

Connecting the VFB pin to VIN configures a phase as a

subordinary phase. The MODE becomes a clock input,

and the voltage control loop is disabled. The subordinary

phase current control loop is still active, and the peak

current is controlled via the shared COMP node.

The phasing of a subordinary phase relative to the main

phase is programmed with a resistor divider on the RT

pin. The use of 1% resistors is recommended. See Table 4

for more information. Figure 17 shows an example.

Table 4. Subordinary Phase Shift Related to MODE Input

PHASE ANGLE BETWEEN

SUBORDINARY

MODULE AND MODE INPUT (°)

RT RESISTOR TO VIN

(Ω)

0

0

90

3M

120

1.4M

180

(RT = GND)

240

715k

270

332k

Application Note 77 provides a detailed explanation of mul-

tiphase operation. The input RMS ripple current cancellation

mathematical derivation are presented, and a graph is dis-

played representing the RMS ripple current reduction as a

function of the number of interleaved phases (see Figure 1).

DUTY CYCLE (VOUT/VIN)

0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9

0.60

0.55

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

47101 F01

6-PHASE

4-PHASE

3-PHASE

2-PHASE

1-PHASE

Figure 1. Input RMS Current Ratios to DC Load

Current as a Function of Duty Cycle