LTM8063 datasheet(13/26 Pages) AD

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LTM4709

Rev. 0

For more information www.analog.com

LTM4709

IMONR1

PGR1

VO11

VIOC1

VO10

PG1

VO12

EN1

BIAS1

VOUTS1

VIN1

GND

VREF1

VOUT1

3.3VBIAS

100 F

4.7 F

4709 F03

22 F

0.8VOUT1

VFB

VIN

IMON1

UPSTREAM

SWITCHING

REGULATOR

0.8V

–

×1

Figure 3. Programming Input-to-Output Difference

Furthermore, if the LTM4709 EN pin shorts to GND, the

LTM4709 input voltage can rise up to the switcher’s

input voltage, and thus potentially exceed the LTM4709’s

absolute maximum rating. To prevent this, the maximum

LTM4709 input voltage VMAXLDOIN can be set using a

resistor R3 between the VIOC1 and the input pin of the

LTM4709 (see Equation 2).

VMAXLDOIN = VREFSW • R1 + R2 + R3

(2)

The VIOC1 pin is capable of sourcing 200μA. Choose R1

and R3 values such that the VIOC1 pin sources at least

10μA to ensure system stability. See Figure 17 for a typical

application to use an upstream switching regulator and

LTM4709 with VIOC function.

Power Good

The PG1,2,3 pin is an open-drain NMOS output that

actively pulls low if EN is low or if one of the following

fault modes is detected.

• VOUT is less than 93% of VOUT(NOMINAL) on the

rising edge.

• VOUT is less than 90% of VOUT(NOMINAL) on the

falling edge.

• BIAS is less than its undervoltage lockout threshold.

• Junction temperature exceeds 168°C typically.

APPLICATIONS INFORMATION

Stability and Output Capacitance

The LTM4709 feedback loop requires a minimum output

capacitance of 10μF for stability. It is recommended to

mount low ESR X5R or X7R ceramic capacitors close to

the LTM4709 VOUT and GND pins. Use wide copper planes

for VOUT and GND to minimize parasitic inductance. If

possible, mount the module adjacent to the load to min-

imize distributed inductance for optimal load transient

performance. Additional ceramic capacitors distributed

around the load are recommended.

For many applications that LTM4709 best fit, such as

FPGA, ASIC processor, or DSP supplies, typically require

a high-frequency decoupling capacitor network for the

device being powered. This network generally consists

of many low-value ceramic capacitors in parallel. Multiple

low-value capacitors in parallel present a favorable

frequency characteristic that reduces the parasitic

inductance of the capacitors.

Ceramic capacitors are manufactured with a variety of

dielectrics, each with different behavior across tempera-

ture and applied voltage. The most common dielectrics

used are specified with EIA temperature characteristic

codes of Z5U, Y5V, X5R and X7R. The Z5U and Y5V

dielectrics are good for providing high capacitances in

a small package, but they tend to have strong voltage

and temperature coefficients as shown in Figure 4. When

used with a 5V regulator, a 16V 10μF Y5V capacitor can

exhibit an effective value as low as 1μF to 2μF for the DC

bias voltage applied and over the operating temperature

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