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BSP205 датащи(PDF) 4 Page - NXP Semiconductors |
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BSP205 датащи(HTML) 4 Page - NXP Semiconductors |
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4 / 12 page ![]() April 1995 4 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSP205 CHARACTERISTICS Tj =25 °C unless otherwise specified Drain-source breakdown voltage −ID =10 µA; VGS =0 −V(BR)DSS min. 60 V Drain-source leakage current −V DS = 48 V; VGS =0 −IDSS max. 1.0 µA Gate-source leakage current ± VGS = 20 V; VDS =0 ±IGSS max. 100 nA Gate threshold voltage min. max. 1.5 3.5 V V −I D = 1 mA; VDS = VGS −VGS(th) Drain-source ON-resistance typ. max. 7.5 10 Ω Ω −I D = 200 mA ; −VGS = 10 V RDS(on) Transfer admittance min. typ. 60 125 mS mS −ID = 200 mA; −VDS = 15 V Yfs Input capacitance at f = 1 MHz; typ. max. 30 45 pF pF −VDS = 10 V; VGS =0 Ciss Output capacitance at f = 1 MHz; typ. max. 20 30 pF pF −VDS = 10 V; VGS =0 Coss Feedback capacitance at f = 1 MHz; typ. max. 5 10 pF pF −VDS = 10 V; VGS =0 Crss Switching times (see Figs 2 and 3) −I D = 200 mA; −VDD = 50 V; −VGS = 0 to 10 V ton typ. max. 3 6 ns ns toff typ. max. 10 15 ns ns |
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