Preliminary Technical Data

AD7367

Rev. PrD | Page 11 of 16

AGND

A

B

SW1

SW2

COMPARATOR

CAPACITIVE

DAC

CONTROL

LOGIC

Figure 4 ADC Conversion Phase

ANALOG INPUTS

Each ADC in the AD7367 has two Single Ended Analog Inputs.

Figure 5 shows the equivalent circuit of the analog input

structure of the AD7367. The two diodes provide ESD

protection. Care must be taken to ensure that the analog input

signals never exceed the supply rails by more than 300 mV. This

causes these diodes to become forward-biased and starts

conducting current into the substrate. These diodes can

conduct up to 10 mA without causing irreversible damage to

the part. Capacitor C1 in Figure 5 is typically 5 pF and can

primarily be attributed to pin capacitance. The resistors are

lumped components made up of the on resistance of the

switches. The value of these resistors is typically about TBD Ω.

Capacitor C2 is the ADC’s sampling capacitors with a

capacitance of approximately TBD pF for the ±10V input range

and approximately TBD pF for all other input ranges.

D

D

C2

R1

C1

Figure 5 Equivalent Analog Input Structure

The AD7367 can handle true bipolar input voltages. The Analog

input can be set to one of three ranges; ±10V, ±5V, 0-10V. The

logic levels on pins RANGE0 and RANGE1 determine which

input range is selected as outlined in Table 7. These range bits

should not be changed during the acquisition time prior to a

conversion but may change at any other time.

Table 7. Analog Input Range Selection

RANGE1

RANGE0

Range Selected

0

0

±10V

0

1

±5V

1

0

0 to 10V

1

1

Do not program

voltage analog input structures. These supplies must be equal to

or greater than ±11.5V. See Table 6 for the requirements on

these supplies. The AD7367 requires a low voltage 4.75V to 5.25

for the interface power.

Channel selection is made via the ADDR pin as shown in

Table 8. The logic level on the ADDR pin is latched on the rising

edge of BUSY for the next conversion, not the one in progress.

When power is first supplied to the AD7367 the default channel

Table 8. Channel Selection

ADDR

Channels Selected

0

1

Transfer Function

The AD7367 output coding is two’s complement. The designed

code transitions occur at successive integer LSB values (i.e. 1

LSB, 2 lSB, and so on). The LSB size is dependant on the analog

input range selected.

Table 9 LSB sizes for each Analog Input Range.

Input Range

Full Scale Range/4096

LSB Size

±10 V

20 V/16384

1.22mV

±5 V

10 V/16384

0.61mV

0 to 10 V

10V/16384

0.61mV

The ideal transfer characteristic is shown in Figure 6

000...000

ANALOG INPUT

011...111

100...001

100...010

011...110

000...001

111...111

+FSR/2 - 1LSB

100...000

0V

Figure 6.Transfer Characteristic