AD15452

Rev. 0 | Page 14 of 16

TIMING

Data from each ADC is serialized and provided on a separate

channel. The data rate for each serial stream is equal to 12 bits

times the sample clock rate, with a maximum of 780 MHz

(12 bits × 65 MSPS = 780 MHz). The lowest typical conversion rate

is 10 MSPS.

Two output clocks are provided to assist in capturing data from

the AD15452. The DCO is used to clock the output data and is

equal to six times the sampling clock (CLK) rate. Data is

clocked out of the AD15452 and can be captured on the rising

and falling edges of the DCO that supports double-data rate

(DDR) capturing. The frame clock out (FCO) is used to signal

the start of a new output byte and is equal to the sampling clock

rate. See the timing diagram shown in Figure 2 for more

information.

DTP PIN

The digital test pattern (DTP) pin can be enabled for two different

types of test patterns. When the DTP is tied to AVDD/3, all the

ADC channel outputs shift out the 1000 0000 0000 pattern. When

the DTP is tied to 2 × AVDD/3, all the ADC channel outputs shift

out the 1010 1010 1010 pattern. The FCO and DCO outputs still

work as usual while all channels shift out the test pattern. This

pattern allows the user to perform timing alignment adjustments

between the DCO and the output data. For normal operation, this

pin should be grounded to AGND.

POWER-DOWN MODE

By asserting the PDWN pin high, the AD15452 is placed in

power-down mode with a typical power dissipation of 360 mW.

During power-down, the LVDS output drivers are placed in a

high impedance state. To return the AD15452 to normal

operating mode, reassert the PDWN pin low.

In power-down mode, low power dissipation is achieved by

shutting down the reference, reference buffer, PLL, and biasing

networks. The decoupling capacitors on REFT and REFB are

discharged when entering standby mode and then must be

recharged when returning to normal operation. As a result, the

wake-up time is related to the time spent in the power-down

mode and shorter cycles result in proportionally shorter wake-

up times. With the recommended 0.1 μF and 10 μF decoupling

capacitors on REFT and REFB, it takes approximately one

second to fully discharge the reference buffer decoupling

capacitors and 3 ms to restore full operation.

POWER SUPPLIES

The nominal setting for the AVDD, PLLVDD, and DRVDD

supplies is 3.3 V. The AVDD and PLLVDD supplies (analog)

should be kept separate from the DRVDD supply (digital).

AVDD and PLLVDD can be tied together as long as clean

supplies are used.

Power supply decoupling capacitors should be used to decouple

the supplies at the board connections. Internal decoupling is

present in the AD15452 and any external decoupling capacitors

should be placed as close to the AD15452 supply pins as

possible.

Both the analog and digital ground pins are used to dissipate

power from the AD15452’s package. These ground pins should

be brought to a ground plane in order to maximize the thermal

dissipation designed into the package.

Table 7. Digital Test Pattern Pin Settings

Selected DTP

DTP Voltage

Resulting D1+, D1–

Resulting FCO and DCO

Normal Operation

AGND

Normal operation

Normal operation

DTP1

AVDD/3

1000 0000 0000

Normal operation

DTP2

2 × AVDD/3

1010 1010 1010

Normal operation

Restricted

AVDD

NA

NA