AD5372/AD5373

Preliminary Technical Data

Rev. P

rF| Page 12 of 25

FUNCTIONAL DESCRIPTION

DAC ARCHITECTURE—GENERAL

The ADAD5372/AD5373 contains 32 DAC channels and 32

output amplifiers in a single package. The architecture of a

single DAC channel consists of a 16-bit (AD5372) or 14-bit

(AD5373) resistor-string DAC followed by an output buffer

amplifier. The resistor-string section is simply a string of

architecture guarantees DAC monotonicity. The 16-bit

(AD5372) or 14-bit (AD5373) binary digital code loaded to the

DAC register determines at which node on the string the

voltage is tapped off before being fed into the output amplifier.

The output amplifier multiplies the DAC out voltage by 4. The

output span is 12 V with a 3 V reference and 20 V with a 5 V

reference.

CHANNEL GROUPS

The 32 DAC channels of the AD5372/AD5373 are arranged

into four groups of 8 channels. The eight DACs of Group 0

derive their reference voltage from VREF0. Group 1 to Group 3

derive their reference voltage from VREF1. Each group has its

own signal ground pin.

Table 6. AD5372(AD5373) Registers

Register Name

Word Length (Bits)

Description

X1A (group)(channel)

16(14)

Input data register A, one for each DAC channel.

X1B (group) (channel)

16(14)

Input data register B, one for each DAC channel.

M (group) (channel)

16(14)

Gain trim registers, one for each DAC channel.

C (group) (channel)

16(14)

Offset trim registers, one for each DAC channel.

X2A (group)(channel)

16(14)

Output data register A, one for each DAC channel. These registers store the final,

calibrated DAC data after gain and offset trimming. They are not readable, nor directly

writable.

X2B (group) (channel)

16(14)

Output data register B, one for each DAC channel. These registers store the final,

calibrated DAC data after gain and offset trimming. They are not readable, nor directly

writable.

DAC (group) (channel)

Data registers from which the DACs take their final input data. The DAC registers are

updated from the X2A or X2B registers. They are not readable, nor directly writable.

OFS0

14

Offset DAC 0 data register, sets offset for Group 0.

OFS1

14

Offset DAC 1 data register, sets offset for Groups 1 to 3.

Control

3

Bit 2 = A/B. 0 = global selection of X1A input data registers. 1 = X1B registers.

Bit 1 = Enable Temp Shutdown. 0 = disable temp shutdown. 1 = enable.

Bit 0 = Soft Power Down. 0 = soft power up. 1 = soft power down.

A/B Select 0

8

Each bit in this register determines if a DAC in Group 0 takes its data from register

X2A or X2B (0 = X2A, 1 = X2B)

A/B Select 1

8

Each bit in this register determines if a DAC in Group 1 takes its data from register

X2A or X2B (0 = X2A, 1 = X2B)

A/B Select 2

8

Each bit in this register determines if a DAC in Group 2 takes its data from register

X2A or X2B (0 = X2A, 1 = X2B)

A/B Select 3

8

Each bit in this register determines if a DAC in Group 3 takes its data from register

X2A or X2B (0 = X2A, 1 = X2B)