32-Channel, 16/14, Serial Input,

Voltage-Output DACs

Preliminary Technical Data

AD5372/AD5373

Rev. P

rF

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FEATURES

32-channel DAC in 56-LFCSP and 64-LQFP

AD5372 Guaranteed monotonic to 16 bits

AD5373 Guaranteed monotonic to 14 bits

Nominal output voltage range of -4 V to +8 V

Multiple, independent output spans available

System calibration function allowing user-programmable

offset and gain

Channel grouping and addressing features

Thermal Monitoring Function

DSP/microcontroller-compatible serial interface

2.5 V to 5.5 V JEDEC-compliant digital levels

Power-on reset

Digital reset (RESET)

Clear function to user-defined SIGGND (CLR pin)

Simultaneous update of DAC outputs (LDAC pin)

APPLICATIONS

Level setting in automatic test equipment (ATE)

Variable optical attenuators (VOA)

Optical switches

Industrial control systems

Instrumentation

FUNCTIONAL BLOCK DIAGRAM

CONTROL

REGISTER

STATE

MACHINE

n

POWER-ON

RESET

SYNC

SDI

SCLK

SDO

BUSY

RESET

CLR

AD5372/

AD5373

SERIAL

INTERFACE

n

VOUT8

VOUT9

VOUT10

VOUT11

VOUT12

VOUT13

VOUT14

VOUT15

SIGGND1

DAC 0

REGISTER

n

n

8

8

TO

MUX 2's

A/B SELECT

REGISTER

MUX

2

X2A REGISTER

X2B REGISTER

OFS1

REGISTER

14

n

DAC 0

OUTPUT BUFFER

AND POWER

DOWN CONTROL

OUTPUT BUFFER

AND POWER

DOWN CONTROL

OFFSET

DAC 1

BUFFER

DAC 7

REGISTER

n

n

MUX

2

X2A REGISTER

X2B REGISTER

DAC 7

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GROUP 1

VREF0

SIGGND0

SIGGND2

SIGGND3

VOUT0

VOUT1

VOUT2

VOUT3

VOUT4

VOUT5

VOUT6

VOUT7

VOUT16

TO

VOUT31

GROUP 2 TO GROUP 3

ARE IDENTICAL TO GROUP 1

LDAC

DAC 0

REGISTER

n

n

8

8

TO

MUX 2's

A/B SELECT

REGISTER

MUX

2

X2A REGISTER

X2B REGISTER

OFS0

REGISTER

14

n

DAC 0

OUTPUT BUFFER

AND POWER

DOWN CONTROL

OUTPUT BUFFER

AND POWER

DOWN CONTROL

OFFSET

DAC 0

BUFFER

GROUP 0

·

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DAC 7

REGISTER

n

n

MUX

2

X2A REGISTER

X2B REGISTER

DAC 7

BUFFER

VREF1

5372-0001B

VREF1 SUPPLIES

GROUP 1 TO 3

n = 16 FOR AD5372

n = 14 FOR AD5373

n

n

n

n

n

n

n

A/B

MUX

X1 REGISTER

MREGISTER

CREGISTER

n

n

n

n

n

n

n

A/B

MUX

X1 REGISTER

MREGISTER

CREGISTER

n

n

n

n

n

n

n

A/B

MUX

X1 REGISTER

MREGISTER

CREGISTER

n

n

n

n

n

n

n

A/B

MUX

X1 REGISTER

MREGISTER

CREGISTER

Figure 1.

AD5372/AD5373—Protected by U.S. Patent No. 5,969,657; other patents pending