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CS5305

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In a similar manner, if the current information is too large,

the COMP voltage will rise to compensate. Again, a square

wave is preferable to a slow change in the COMP voltage,

and placing a capacitor between VDRP and COMP will

“square up” the COMP waveform as shown in Figure 44.

Figure 44.

Current Transient

COMP Ideal Waveform

COMP Uncorrected

Waveform

VOUT Uncorrected

Waveform

COMP Corrected

Waveform

VOUT Corrected

Waveform

Once the COMP waveform has been squared up, it is

necessary to check the VDRP waveform. The VDRP

waveform is dependent on the choice of ramp

components. If these components have been chosen such

that (RCSx)(CCSx) = L / ESRL, the VDRP waveform should

be a square wave that matches the current step. At this

point, the VOUT waveform should also be a square wave

and transient performance should be optimized.

If (RCSx)(CCSx) < L / ESRL, the VDRP waveform will be

faster than current step. The VDRP voltage will exhibit a fast

rise followed by an exponential droop down to a DC level,

as shown in Figure 45. This waveform has the effect of

telling the system that transient current signals are larger

than the true current. Response will be slowed, and VOUT

will overshoot until the error amplifier “catches up”. In this

case, it is desirable to push the VFB pin down, so that COMP

voltage is forced up and duty cycle is reduced slightly. This

is done by placing a series RC filter across resistor RFB.

Figure 45.

Current Step

VDRP

(RCSx)(CCSx) < L/ESRL

If (RCSx)(CCSx) > L / ESRL, the VDRP waveform will be

slower than the current step. VDRP will exhibit an initial

spike, but the voltage will then exponentially rise toward its

correct DC level, as shown in Figure 46. This waveform

effectively tells the system that the current signal is smaller

than the true current, and response will be faster than

optimal. VOUT will then undershoot. In this case, forcing

VFB up so COMP voltage decreases results in increasing

output duty cycle. The series RC filter is now located in

parallel with RDRP.

Figure 46.

Current Step

VDRP

(RCSx)(CCSx) > L/ESRL

These components are chosen empirically. The fastest

way to optimize the design is to start with a 1 nF capacitor

and a 500 kΩ potentiometer and “dial in” performance.

Error Amplifier Compensation

Error amplifier compensation is very simple using the

enhanced V2 control architecture. A single 0.1 μF capacitor

from the COMP lead to ground is usually sufficient. As an

alternative, a resistor and capacitor in series between COMP

and ground may improve output voltage positioning during

current transients. The resistance will speed up the effective

slew rate of the error amplifier output.

The COMP capacitor also provides soft start and

hiccup−mode timing. At start−up, the COMP capacitance

must charge from ground through a typical channel start−up

offset of 0.6 V before the GATE outputs are allowed to begin

switching. The COMP capacitance includes both the COMP

capacitor and any droop compensation capacitance that may

be connected to the COMP pin. The typical soft start time

can then be approximated as:

TSOFT−START(ms) + 20 CCOMP(TOTAL)(mF)

Hiccup timing has a similar equation. During

hiccup−mode, the COMP voltage traverses between the

fault reset threshold (approximately 0.2 V) and the channel

start−up offset voltage. When the fault circuitry becomes

active, the COMP capacitor is discharged with a 5 μA

current until the fault reset threshold is reached. The time

this initial discharge takes is variable depending on the

COMP voltage when the fault occurred. Once the reset

threshold is reached, the COMP capacitor is charged with

the 30 μA current until the start−up offset voltage is reached.

The GATE outputs will begin to pulse, quickly ramping the

inductor current. The fault circuitry can then re−detect the

fault condition some number of GATE pulses later if it is still

present. Thus, the period of the fault hiccup mode is

approximately defined as:

THICCUP(ms) + 93.3 CCOMP(TOTAL)(mF)

Period is only approximately defined since the number of

GATE pulses between restart and redetection of a fault

condition is unpredictable.

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