CS5305 datasheet(16/33 Pages) ONSEMI

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CS5305

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APPLICATIONS INFORMATION

THEORY OF OPERATION

Fixed Frequency Multi−phase Control

Multi−phase CPU controllers include the necessary control

circuitry to implement several buck converters in parallel.

These converters are configured to turn on at different times.

This allows much higher output current than could be

provided by a single converter. The apparent ripple frequency

is increased and so output current can ramp up or down faster

than a single converter with the same value of output

inductor. Heat is also spread among multiple components.

The CS5305 uses a fixed frequency, Enhanced V2

architecture. Each phase is delayed by approximately 120°

from the previous phase. The GATE output for each channel

changes to a logic high at the beginning of its oscillator cycle.

Inductor current ramps up until the combination of the current

sense signal and the output ripple trip the PWM comparator,

at which time the GATE output changes to a logic low. Once

low, the GATE output remains low until the next oscillator

cycle begins, and the control loop will not respond until that

time. The Enhanced V2 control loop will respond to line and

load transients while the GATE output is high. Enhanced V2

control will respond within the off time of the converter.

PWM

COMP

−

OFFSET

CS AMP

−

ERROR

AMP

−

CSx

CSREF

COMP

VFB

RCSx

CCSx

CCOMP

ESRL

SWITCH

VOUT

NODE

Figure 27.

The Enhanced V2 architecture measures and adjusts

current in each phase. An additional input (CSx pin)

provides current information for each output phase to the

control loop as shown in Figure 27. Inductor current is

measured across capacitor Ccsx. The voltage across this

capacitor is equal to the product of the output current and the

inductor ESR if these components are chosen such that

(Ccsx)(Rcsx) = (L)/ESRL. This signal is buffered by the

current sense amplifier (unity gain in the CS5305) and

summed with an offset voltage before it is presented as input

to non−inverting input of the PWM comparator. Inductor

current provides the PWM ramp. As inductor current

increases, the voltage at the positive input to the PWM

comparator rises and terminates the PWM cycle. If the

inductor starts the next cycle with higher current, the PWM

cycle terminates earlier, thus providing negative feedback.

A CSx input is provided for each channel, but the CSREF,

VFB and COMP inputs are common to all phases. Current

sharing between phases is accomplished by referencing all

phases to the same error amplifier. Any phase with a larger

current signal will turn off earlier than the channels with a

lower current signal.

Including both current and voltage information in the

feedback signal allows the open loop output impedance of the

power stage to be controlled. In the absence of any load

current, the COMP pin voltage will be equal to the sum of the

output voltage, the offset voltage and half of the steady−state

ramp voltage. (At no load, the output ripple current’s positive

and negative contributions are equal, and the DC averaged

voltage is equal to half the ripple voltage.) If the COMP pin

is held steady and the inductor current is forced to change, the

output voltage will also change. In a closed−loop situation,

changing the inductor current will force the COMP voltage to

change so the output voltage can remain the same. The change

in COMP voltage depends on the scaling of the current

feedback signal, and can be defined as:

DVCOMP + (ESRL)(Current Sense Gain)(DIPHASE)

Since the current sense gain for this loop is unity, this

equation reduces to:

DVCOMP + (ESRL)(DIPHASE)

and so the single−phase power stage output impedance is:

DVCOMP DIPHASE + ESRL

The CS5305 has three phases, so the total power stage

output impedance is then ESRL/3.

Lossless Inductive Current Sensing

Current can be sensed across the inductor as shown in

Figure 27. The output inductor is designated L and the

inductor’s equivalent series resistance is designated ESRL.

In the ideal case, the values of Rcsx and Ccsx are chosen

such that (L/ESRL) = (Rcsx)(Ccsx). If this criterion is met,

the current sense signal will have the same shape as the

inductor current, and the circuit can be analyzed as if a sense

resistor with value equal to ESRL was placed in series with

the inductor. However, these components also determine the

ramp signal that is used to prevent pulse skipping and duty

cycle jitter. Choosing (Rcsx)(Ccsx) < (L/ESRL) will result

in the AC portion of the current sense signal being scaled

more than the DC portion. This results in a larger ramp

signal, but the current signal will overshoot during

transients. This will affect transient response, adaptive

voltage positioning and current limit. The COMP pin

voltage will overshoot along with the current signal in order

to maintain the output voltage. The COMP voltage will

eventually find the correct level for regulation, but the error

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