CS5303 datasheet(14/19 Pages) ONSEMI

14 / 19 page

CS5303

http://onsemi.com

disabled or will only check that the applicable supply is on

− not that it is at a high enough voltage to run the converter.

For the 12 VIN converter in the application diagram on

page 2 the UVLO pin for the high side driver is pulled up

by the 5 V supply (through two diode drops) and the function

is not used. The diode between the COMP pin and the 12 V

supply holds the COMP pin near Gnd and prevents start−up

while the 12 V supply is off. In an application where a higher

UVLO threshold is necessary a circuit like the one in Figure

15 will lock out the converter until the 12 V supply exceeds

9 V.

Figure 15. External UVLO Circuit

COMP

100 k

50 k

+5 V

+12 V

Layout Guidelines

With the fast rise, high output currents of microprocessor

applications parasitic inductance and resistance should be

considered when laying out the power, filter and feedback

signal sections of the board. Typically a multi−layer board

with at least one ground plane is recommended. If the layout

is such that high currents can exist in the ground plane

underneath the controller or control circuitry, the ground

plane can be slotted to reroute the currents away from the

controller. The slots should typically not be placed between

the controller and the output voltage or in the return path of

the gate drive. Additional power and ground planes or

islands can be added as required for a particular layout.

Output filter components should be placed on wide planes

connected directly to the load to minimize resistive drops

during heavy loads and inductive drops and ringing during

transients. If required, the planes for the output voltage and

return can be interleaved to minimize inductance between

the filter and load.

Voltage feedback should be taken from a point of the

output or the output filter that doesn’t favor any one phase.

If the feedback connection is closer to one inductor than the

others the ripple associated with that phase may appear

larger than the ripple associated with the other phases and

poor current sharing can result.

The current sense signal is typically tens of milli−volts.

Noise pick−up should be avoided wherever possible.

Current feedback traces should be routed away from noisy

areas such as switch nodes and gate drive signals. The paths

should be matched as well as possible. It is especially

important that all current sense signals be picked off at

similar points for accurate current sharing. If the current

signal is taken from a place other than directly at the inductor

any additional resistance between the pick−off point and the

inductor appears as part of the inherent inductor resistance

and should be considered in design calculations. Capacitors

for the current feedback networks should be placed as close

to the current sense pins as practical.

DESIGN PROCEDURE

Current Sensing, Power Stage and

Output Filter Components

1. Choose the output filter components to meet peak

transient requirements. The formula below can be

used to provide an approximate starting point for

capacitor choice, but will be inadequate to calculate

actual values.

DVPEAK + (DI DT)

ESL ) DI

ESR

Ideally the output filter should be simulated with

models including ESR, ESL, circuit board parasitics

and delays due to switching frequency and converter

response.

Typically

both

bulk

capacitance

(electrolytic, Oscon, etc,) and low impedance

capacitance (ceramic chip) will be required. The bulk

capacitance provides “hold up” during the converter

response. The low impedance capacitance reduces

steady state ripple and bypasses the bulk capacitance

during slewing of output current.

2. For inductive current sensing (only) choose the

current sense network RC to provide a 25 mV

minimum ramp during steady state operation.

R + (VIN * VOUT)

VOUT VIN

25 mV

Then choose the inductor value and inherent

resistance to satisfy L/RL = R × C.

For ideal current sense compensation the ratio of L

and RL is fixed, so the values of L and RL will be a

compromise typically with the maximum value RL

limited by conduction losses or inductor temperature

rise and the minimum value of L limited by ripple

current.

3. For resistive current sensing choose L and RS to

provide a steady state ramp greater than 25 mV.

L RS + (VIN * VOUT)

TON 25 mV

Again the ratio of L and RL is fixed and the values of

L and RS will be a compromise.

4. Calculate the high frequency output impedance

(ConverterZ) of the converter during transients. This

is the impedance of the Output filter ESR in parallel

with the power stage output impedance (PwrstgZ)

and will indicate how far from the original level

(ΔVR) the output voltage will typically recover to

within one switching cycle. For a good transient

response ΔVR should be less than the peak output

voltage overshoot or undershoot.

CS5303 датащи(PDF) 14 Page - ON Semiconductor

CS5303 датащи(HTML) 14 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

датащи скачать

ссылки URL