CS5165A

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Figure 24. Power Good Response to an Out of

Regulation Condition

Trace 2− PWRGD (2.0 V/div.)

Figure 24 shows the relationship between the regulated

Power Good from interrupting the CPU unnecessarily, the

from toggling Power Good. The internal time delay is designed

to take about 75

ms for Power Good to go low and 65 ms for it

to recover. This allows the Power Good signal to be completely

insensitive to out of regulation conditions that are present for

a duration less than the built in delay (see Figure 25).

It is therefore required that the output voltage attains an out

of regulation or in regulation level for at least the built−in delay

time duration before the Power Good signal can change state.

Figure 25. Power Good is Insensitive to Out of

Regulation Conditions that are Present for a

Duration Less Than the Built In Delay

Trace 2− PWRGD (2.0 V/div.)

Selecting External Components

The CS5165A buck regulator can be used with a wide range

of external power components to optimize the cost and

performance of a particular design. The following information

can be used as general guidelines to assist in their selection.

NFET Power Transistors

Both logic level and standard FETs can be used. The

reference designs derive gate drive from the 12 V supply

which is generally available in most computer systems and

utilize logic level FETs. A charge pump may be easily

implemented to support 5.0 V only systems. Multiple FET’s

may be paralleled to reduce losses and improve efficiency and

thermal management.

Voltage applied to the FET gates depends on the application

circuit used. Both upper and lower gate driver outputs are

specified to drive to within 1.5 V of ground when in the low

state and to within 2.0 V of their respective bias supplies when

in the high state. In practice, the FET gates will be driven rail

to rail due to overshoot caused by the capacitive load they

present to the controller IC. For the typical application where

output current, the following gate drive is provided:

VGS(BOTTOM) + 12 V

VGS(TOP) + 12 V * 5.0 V + 7.0 V

(see Figure 26)

Figure 26. Gate Drive Waveforms Depicting

Rail to Rail Swing

Trace 3− GATE(H) (10 V/div.)

Trace 4− GATE(L) (10 V/div.)

Trace 2− Inductor Switching Node (5.0 V/div.)