CDP1802AC/3

FN1441 Rev 3.00

Page 23 of 27

October 17, 2008

TABLE 5. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES

STATE

I

N

SYMBOL

OPERATION

DATA

BUS

MEMORY

ADDRESS

MRD

MWR

N

LINES

NOTES

S1

RESET

0

 I, N, Q, X, P; 1 lE

00

XXXX

1

1

0

17

Initialize, Not Programmer

Accessible

0000

 R

00

XXXX

1

1

0

18

S0

FETCH

MRP

 l, N; RP + 1  RP

MRP

RP

0

1

0

19

S1

0

0

lDL

IDLE

MR0

RO

0

1

0

20, Fig. 6

0

1 - F

LDN

MRN

 D

MRN

RN

0

1

0

Fig. 6

1

0 - F

INC

RN + 1

 RN

Float

RN

1

1

0

Fig. 4

2

0 - F

DEC

RN - 1

 RN

Float

RN

1

1

0

Fig. 4

3

0 - F

Short Branch Taken: MRP

 RP.0

Not Taken; RP + 1

 RP

MRP

RP

0

1

0

Fig. 6

4

0 - F

LDA

MRN

 D; RN + 1  RN

MRN

RN

0

1

0

Fig. 6

5

0 - F

STR

D

 MRN

D

RN

1

0

0

Fig. 5

60

IRX

RX + 1

 RX

MRX

RX

0

1

0

Fig. 5

61

OUT 1

MRX

 BUS; RX + 1  RX

MRX

RX

0

1

1

Fig. 9

2

OUT 2

2

Fig. 9

3

OUT 3

3

Fig. 9

4

OUT 4

4

Fig. 9

5

OUT 5

5

Fig. 9

6

OUT 6

6

Fig. 9

7

OUT 7

7

Fig. 9

9

INP 1

BUS

 MRX, D

Data from

I/O Device

RX

1

0

1

Fig. 8

A

INP 2

2

Fig. 8

B

INP 3

3

Fig. 8

C

INP 4

4

Fig. 8

D

INP5

5

Fig. 8

E

INP6

6

Fig. 8

F

INP7

7

Fig. 8

70

RET

MRX

 (X, P); RX + 1  RX;

1

 lE

MRX

RX

0

1

0

Fig. 6

1

DlS

MRX

 (X, P); RX + 1  RX;

0

 lE

MRX

RX

0

1

0

Fig. 6

2

LDXA

MRX

 D; RX + 1  RX

MRX

RX

0

1

0

Fig. 6

3

STXD

D

 MRX; RX - 1  RX

D

RX

1

0

0

Fig. 5

4

ADC

MRX + D + DF

 DF, D

MRX

RX

0

1

0

Fig. 6

5

SDB

MRX - D - DFN

 DF, D

MRX

RX

0

1

0

Fig. 6

6

SHRC

LSB(D)

 DF; DF  MSB(D)

Float

RX

1

1

0

Fig. 4

7

SMB

D - MRX - DFN

 DF, D

MRX

RX

0

1

0

Fig. 6

8

SAV

T

 MRX

T

RX

1

0

0

Fig. 5