CDP1802AC/3

FN1441 Rev 3.00

Page 8 of 27

October 17, 2008

NOTES:

8. This timing diagram is used to show signal relationships only and does not represent any specific machine cycle.

9. All measurements are referenced to 50% point of the waveforms.

10. Shaded areas indicate “Don’t Care” or undefined state. Multiple transitions may occur during this period.

Timing Waveforms (Continued)

CLOCK

TPA

TPB

MEMORY

MRD

MWR

(I/O EXECUTION

Q

DATA FROM

DMA

INTERRUPT

EF 1-4

WAIT

CLEAR

REQUEST

REQUEST

BUS TO CPU

N0, N1, N2

STATE

DATA FROM

CPU TO BUS

(MEMORY

WRITE CYCLE)

(MEMORY

ADDRESS

READ CYCLE)

CODES

CYCLE)

tW

00

10

20

30

40

50

60

70

00

01

11

21

31

41

51

61

71

01

0

1

2

3

4

5

6

7

0

tPLH

tPHL

tPLH

tPHL

tPLH, tPHL

tSU

tH

ADDRESS BYTE

HIGH ORDER

tPHL

tPLH

tSU

tPLH, tPHL

tPLH, tPHL

tPLH

tH

tPLH

tH

tPLH, tPHL

tPLH, tPHL

tPLH, tPHL

ADDRESS BYTE

LOW ORDER

tPHL

tPLH

tPHL

tPLH

tPHL

tPLH

tPLH

DATA

LATCHED IN CPU

tSU

tH

tSU

tH

tSU

tH

INTERRUPT

SAMPLED (S1, S2)

FLAG LINES

SAMPLED (IN S1)

ANY NEGATIVE

TRANSITION

tSU

tW

tSU

tH

FIGURE 2. TIMING WAVEFORM

DMA SAMPLED (S1, S2, S3)