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January 18, 2011

CPS-10Q

CPS-10Q Datasheet

2010 Integrated Device Technology, Inc. All rights reserved.

11 Device Performance Figures

11.1 Performance Figures

The following table lists the CPS-10Q’s performance figures. Figures provided here are guaranteed by design and characterization, but are not

production tested.

Notes:

1. Values are guaranteed by characterization, but are not production tested.

2. For those specifications associated with an sRIO transaction, it should be noted that the upper limit to a specification may be dictated by sRIO priority handling. For

example, a maintenance read packet having lower priority may be held off until higher priority packets in queue are serviced. The user should take into consideration

this additional priority-induced delay when examining these specifications. I2C and JTAG configuration register access transactions are always deterministic and

follow these specifications identically.

3. “Cycles” refer to internal core clock cycles which are two times the external reference clock (REF_CLK) frequency = 312.5 MHz.

Description

Min

Typ

Max

Units

Comments

Throughput (Peak)

__

__

100

Gbps

Throughput (Sustained)

__

80

__

Gbps

Value shown is for device configured for 10 4X ports, each run-

ning at 3.125Gbps, 276 byte packets at priority 0. Please contact

IDT technical support for figures related to a specific usage case

and traffic conditions.

Per Port throughput (Peak)

__

__

10

Gbps

Value shown is for device configured for each port with 4X

3.125G mode. The sustained throughput is shown in other table

below.

Switch Latency Jitter (70% switch load)(2)

__

60

__-ns

Latency Jitter for the switch lock is the sum of the Physical layer

jitter plus one maintenance packet of contention delay for a

given output port. Worst case for the physical layer is the jitter

caused by the port sync process. This requires 6 32-bit control

symbols plus 2 cycle times the port rate. The figures shown here

are for priority 2 packets under 70% switch loading with an even

mix of packets of each priority. It assumes that no maintenance

packets contend on the output port.

Soft Reset to Receipt of Valid Packets

__

__

26

us

This includes reset time as well as link establishment.

Hard Reset to Receipt of Valid Packets

__

__

26

us

This includes reset time as well as link establishment.

Multicast Map Update Delay

25

__

2000

cycles(3)

Table 4 80KSW0005 Performance Figures