10

Integrated

Circuit

Systems, Inc.

ICS951413

0929D—10/30/06

SMBus Table: SRCCLK(7:3,0), CLKREQA# Output Control Register

Pin #

Name

Control Function

Type0

1

PWD

Bit 7

SRCCLK7

RW

Disable

Enable

1

Bit 6

SRCCLK6

RW

Disable

Enable

1

Bit 5

SRCCLK5

RW

Disable

Enable

1

Bit 4

SRCCLK4

RW

Disable

Enable

1

Bit 3

SRCCLK3

RW

Disable

Enable

1

Bit 2

SRCCLK0

RW

Disable

Enable

1

Bit 1

REQASRC3

CLKREQA# Controls

SRC3

RW

Does not

control

Controls

0

Bit 0

REQASRC0

CLKREQA# Controls

SRC0

RW

Does not

control

Controls

0

SMBus Table: SRCCLK(3,0), ATIGCLK Output Control Register

Pin #

Name

Control Function

Type

0

1

PWD

Bit 7

REQASRC7

CLKREQA# Controls

SRC7

RW

Does not

control

Controls

0

Bit 6

REQASRC6

CLKREQA# Controls

SRC6

RW

Does not

control

Controls

0

Bit 5

REQASRC5

CLKREQA# Controls

SRC5

RW

Does not

control

Controls

0

Bit 4

REQASRC4

CLKREQA# Controls

SRC4

RW

Does not

control

Controls

0

Bit 3

ATIGCLK1

RW

Disabled

Enabled

1

Bit 2

ATIGCLK0

RW

Disabled

Enabled

1

Bit 1

Differential

Output Disable

Mode

Hi-Z or driven when

disabled

RW

Driven

Hi-Z

0

Bit 0

USB_48Str

48MHz Strength Control

RW

1X

2X

1

NOTE: Do NOT simultaneously select CLKREQA# and CLKREQB# to control an SRC output.

Behavior of the device is undefined under these conditions.

SMBus Table: Output Drive and ATIG Frequency Control Register

Pin #

Name

Control Function

Type

0

1

PWD

Bit 7

REF2Str

REF2 Strength Control

RW

1X

2X

1

Bit 6

CPU2_Stop_En

RW

Free-Run

Stoppable

1

Bit 5

CPU1_Stop_En

RW

Free-Run

Stoppable

1

Bit 4

SRCFS4

(SS_EN)

Freq Select Bit 4

(SS_EN)

RW

0

Bit 3

SRCFS3

Freq Select Bit 3

RW

0

Bit 2

SRCFS2

Freq Select Bit 2

RW

0

Bit 1

SRCFS1

Freq Select Bit 1

RW

0

Bit 0

SRCFS0

Freq Select Bit 0

RW

0

NOTE: CPU(1:2)_Stop_En (Byte5, bit 6:5) only exist in devices with REV ID = 2 or higher

Output Enable

These outputs cannot

be controlled by

CLKREQ# pins.

30,29

CPU, SRC,

ATIG

4

16,17

18,19

22,23

27,28

24,25

34,33

Byte 4

12,13

Master Output control.

Enables or disables

output, regardless of

CLKREQ# inputs.

16,17

18,19

22,23

24,25

34,33

Byte 3

12,13

Byte 5

52

41,40

43,42

-

See Table 2 SRC

Frequency Selection

-

-

-

-

0 = CPU is free-run

1 = CPU is stopped by

CPU_STOP#