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ICS8714008I датащи(PDF) 21 Page - Renesas Technology Corp

номер детали ICS8714008I
подробное описание детали  FemtoClock® Zero Delay Buffer/ Clock Generator for PCI Express™ and Ethernet
PDF  35 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

ICS8714008I датащи(HTML) 21 Page - Renesas Technology Corp

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ICS8714008I DATA SHEET
FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET
ICS8714008DKI REVISION A NOVEMBER 25, 2013
21
©2013 Integrated Device Technology, Inc.
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both signals must meet the VPP and VCMR input
requirements. Figures 4A to 4F show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
vendor of the driver component to confirm the driver termination
requirements. For example, in Figure 4A, the input termination
applies for IDT open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
Figure 4A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 4C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 4E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 4B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 4D. CLK/nCLK Input Driven by a 3.3V LVDS Driver
Figure 4F. CLK/nCLK Input Driven by a
3.3V MLVDS Driver
R1
50
Ω
R2
50
Ω
1.8V
Zo = 50
Ω
Zo = 50
Ω
CLK
nCLK
3.3V
LVHSTL
IDT
LVHSTL Driver
Differential
Input
3.3V
CLK
nCLK
3.3V
3.3V
LVPECL
Differential
Input
HCSL
*R3
*R4
CLK
nCLK
3.3V
3.3V
Differential
Input
CLK
nCLK
Differential
Input
LVPECL
3.3V
Zo = 50
Ω
Zo = 50
Ω
3.3V
R1
50
Ω
R2
50
Ω
R2
50
Ω
3.3V
R1
100
Ω
LVDS
CLK
nCLK
3.3V
Receiver
Zo = 50
Ω
Zo = 50
Ω
3.3V
R1
100
Ω
R2
100
Ω
MLVDS
CLK
nCLK
3.3V
Receiver
Zo = 50
Ω
Zo = 50
Ω



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