ICS8714008I DATA SHEET

FEMTOCLOCK® ZERO DELAY BUFFER/CLOCK GENERATOR FOR PCI EXPRESSTM AND ETHERNET

ICS8714008DKI REVISION A NOVEMBER 25, 2013

2

©2013 Integrated Device Technology, Inc.

Block Diagram

PDIV1:0

00 ÷4 (default)

01 ÷5

10 ÷8

11 ÷1

CLK

nCLK

PDIV0

PDIV1

FBI_DIV1:0

00 ÷1

01 ÷2

10 ÷4

11 ÷5 (default)

FBIN

nFBIN

FBI_DIV0

FBI_DIV1

MLVDS

nMLVDS

PD

VCO

490-660MHz

0

1

OE_MLVDS

PLL_SEL

QDIV7

0 ÷4 (default)

1 ÷5

QDIV7 (PD)

Q7

nQ7

QDIV0

0 ÷4 (default)

1 ÷5

QDIV0 (PD)

Q0

nQ0

FBO_DIV

0 ÷4 (default)

1 ÷5

FBO_DIV (PD)

FBOUT

nFBOUT

3

OE2:0 (PU:PU)

1One Master Reset pin (MR) is used to reset all the internal dividers, but the MR lines are not drawn as all tied together to reduce control line clutter, making the block diagram

easier to read.

PU means internal pull-up resistor on pin (power-up default is HIGH if not externally driven)

PD means internal pull-down resistor on pin (power-up default is LOW if not externally driven)

IREF

8 total HCSL Output pairs

MR1

MR1

MR1

MR1

Pulldown

Pulldown

Pulldown

Pulldown

PU/PD

Pulldown

Pulldown

Pulldown

Pulldown

PU/PD

Pullup

Pullup

Pullup

Pullup